公开(公告)号：BR9005533A

公开(公告)日：1991-09-17

申请号：BR9005533

申请日：1990-10-31

Applicant: IBM

Inventor： LYFORD AVERY M ,  MOELLER DENNIS L ,  KLIM PETER J

IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F9/46

Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.