公开(公告)号：DE69223193T2

公开(公告)日：1998-05-20

申请号：DE69223193

申请日：1992-07-10

Applicant: IBM

Inventor： HSIEH CHANG-MING ,  KUMAR SHANTHA ARAKERE ,  HSU LOUIS LU-CHEN ,  TIEN ZU-JEAN TIEN ZU-JEAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

Abstract: A mesa comprising successive layers of bottom SiO2 (22A/32), polysilicon pad (22A), top silicon nitride (26A) is first formed on a semiconductor substrate (20). Next, a first layer (34) of N type polysilicon and a second layer (36) of silicon nitride are conformally deposited thereon. Next, the said second layer is anisotropically etched to leave sidewall spacers (36A). A portion of said first layer at the top of the mesa is now exposed. The said exposed portion is then removed leaving lateral sidewalls (34A), whose top part are oxidized (38). Next, all the silicon nitride material is removed exposing the polysilicon pad (22A) and leaving very narrow sidewall spacers (34A) of N type polysilicon that are used as in-situ masks to deliverate very sub-micronic portions (32A) of the bottom SiO2 layer to be subsequently used as the gate dielectric for the FETs.

公开(公告)号：DE69223193D1

公开(公告)日：1998-01-02

申请号：DE69223193

申请日：1992-07-10

Applicant: IBM

Inventor： HSIEH CHANG-MING ,  KUMAR SHANTHA ARAKERE ,  HSU LOUIS LU-CHEN ,  TIEN ZU-JEAN TIEN ZU-JEAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

Abstract: A mesa comprising successive layers of bottom SiO2 (22A/32), polysilicon pad (22A), top silicon nitride (26A) is first formed on a semiconductor substrate (20). Next, a first layer (34) of N type polysilicon and a second layer (36) of silicon nitride are conformally deposited thereon. Next, the said second layer is anisotropically etched to leave sidewall spacers (36A). A portion of said first layer at the top of the mesa is now exposed. The said exposed portion is then removed leaving lateral sidewalls (34A), whose top part are oxidized (38). Next, all the silicon nitride material is removed exposing the polysilicon pad (22A) and leaving very narrow sidewall spacers (34A) of N type polysilicon that are used as in-situ masks to deliverate very sub-micronic portions (32A) of the bottom SiO2 layer to be subsequently used as the gate dielectric for the FETs.