公开(公告)号：US3474239A

公开(公告)日：1969-10-21

申请号：US3474239D

申请日：1967-01-13

Applicant: IBM

Inventor： ALLEN RICHARD G ,  KURTZ CLARK ,  MACSORLEY OLIN L ,  SPENCER DANA R ,  STETLER WESLEY C

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/57 ,  G06F15/78 ,  G06F5/02 ,  G06F7/385 ,  G06F7/42

CPC classification number: G06F7/57 ,  G06F7/00 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/508 ,  G06F15/78 ,  G06F2207/3824

公开(公告)号：US3626427A

公开(公告)日：1971-12-07

申请号：US3626427D

申请日：1967-01-13

Applicant: IBM

Inventor： MACSORLEY OLIN L ,  HASBROUCK LEO J ,  STETLER WESLEY C ,  HOLLERAN C RICHARD ,  GELLER ALAN R ,  KURTZ CLARK ,  NELSON ROBERT A ,  SMITH GORDON L ,  SPENCER DANA R ,  TIMM JOE F ,  WISSICK WILLIAM P ,  ALLEN RICHARD G ,  DUBOIS THOMAS F ,  HACK GEORGE E ,  ANNUNZIATA EUGENE J ,  HOSKINSON WILLIAM C ,  KING LEWIS E ,  JOHANSEN THORE-JAN

IPC: G06F15/78 ,  G06F9/00 ,  G06F3/00 ,  G06F15/00

CPC classification number: G06F15/78

Abstract: The specification discloses an illustrative embodiment for the invention comprising a large-scale data processing system of the type which is composed of a plurality of quasi-independent units. The environmental data processing system includes a central processing unit or portion, which is herein referred to as a CPU, a plurality of storage units, a plurality of input/output control devices referred to herein as channels, as well as control and maintenance facilities which are found in a power distribution unit, herein referred to as a PDU. The CPU of the environmental system includes a control or instruction unit hereinafter referred to as an I-unit, and an arithmetic and logic or execution unit, hereinafter referred to as an E-unit. The I-unit includes controls for instruction fetching, branching, interruption handling, communication with the input/output channels, and other related functions. The E-unit of the environmental system can perform algebraic and logical operations, moving, shifting, and other functions.

公开(公告)号：US3504167A

公开(公告)日：1970-03-31

申请号：US3504167D

申请日：1967-01-13

Applicant: IBM

Inventor： KURTZ CLARK

IPC: G06F7/52 ,  G06F7/535 ,  G06F7/38

CPC classification number: G06F7/535

公开(公告)号：CA1001237A

公开(公告)日：1976-12-07

申请号：CA183584

申请日：1973-10-17

Applicant: IBM

Inventor： EICHELBERGER EDWARD B ,  GUSTAFSON RICHARD N ,  KURTZ CLARK

IPC: G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037 ,  H03K19/00 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173

公开(公告)号：DE2360762A1

公开(公告)日：1974-07-11

申请号：DE2360762

申请日：1973-12-06

Applicant: IBM

Inventor： EICHELBERGER EDWARD BAXTER ,  GUSTAFSON RICHARD NEIL ,  KURTZ CLARK

IPC: G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037 ,  H03K19/00 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173 ,  H03K19/02 ,  G11C19/00

公开(公告)号：CA889529A

公开(公告)日：1971-12-28

申请号：CA889529D

Applicant: IBM

Inventor： STETLER WESLEY C ,  ALLEN RICHARD G ,  KURTZ CLARK ,  MACSORLEY OLIN L ,  SPENCER DANA R

公开(公告)号：CA886230A

公开(公告)日：1971-11-16

申请号：CA886230D

Applicant: IBM

Inventor： KURTZ CLARK

公开(公告)号：DE1524146B1

公开(公告)日：1970-08-27

申请号：DEI0030507

申请日：1966-04-01

Applicant: IBM

Inventor： KURTZ CLARK

IPC: G06F7/52 ,  G06F7/535 ,  G06F15/78

公开(公告)号：DE1524143A1

公开(公告)日：1970-07-09

申请号：DE1524143

申请日：1966-03-31

Applicant: IBM

Inventor： GEORGE ALLEN RICHARD ,  KURTZ CLARK ,  LOWE MACSORLEY OLIN ,  ROYCE SPENCER DANA ,  CHARLES STETLER WESLEY

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/57 ,  G06F15/78

Abstract: 1,081,665. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 21, 1966 [April 5, 1965], No. 12255/66. Heading G4A. In a data-processing device, a logical function of corresponding portions of two operands is formed and passed through first or second means to an output register, the first means providing the result of an arithmetic operation on the operands and the second performing an operation. Two operands are fed to a bit function generator which produces the AND, OR and OR-E (meaning exclusive-or) of each pair of corresponding bits. For addition, the output of a final sum adder is gated to an output register, the final sum adder being fed with half sums (being the OR-E signals), and carries from a carry look-ahead generator fed by the AND and OR signals. Subtraction is by one's or two's complement addition, involving the inversion of one of the operands before input to the bit function generator, and control of the carry look-ahead generator either to permit end-around carry or to add 1 to the lowest order bit position respectively. For shift, the set of bits to be shifted and a set of all zeroes are supplied as the two operands and the OR-E signals (equalling the bits to be shifted) are gated to the shifter from which (after shifting) they are gated to the output register. The results of the logical operations AND, OR, OR-E are passed to the output register via the shifter (without shifting) by passing to the shifter the AND, AND and OR-E, OR-E signals from the bit function generator respectively. It is mentioned that the shift function may be used in multiplication or division (but no details are given.