Differential mixed signal multiplier with three capacitors

    公开(公告)号:GB2610332B

    公开(公告)日:2024-12-04

    申请号:GB202216836

    申请日:2021-03-01

    Applicant: IBM

    Abstract: A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.

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