公开(公告)号：GB2585992B

公开(公告)日：2021-06-09

申请号：GB202016348

申请日：2019-04-01

Applicant: IBM

Inventor： SEYOUNG KIM ,  TAYFUN GOKMEN

IPC: G06N3/063 ,  G06N3/08

Abstract: Systems and methods are provided to perform weight update operations in a resistive processing unit (RPU) system to update weight values of RPU devices comprising tunable resistive device. A weight update operation for a given RPU device includes maintaining a weight update accumulation value for the RPU device, adjusting the weight update accumulation value by one unit update value in response to a detected coincidence of stochastic bits streams of input vectors applied on an update row and update column control lines connected to the RPU device, generating a weight update control signal in response to the accumulated weight value reaching a predefined threshold value, and adjusting a conductance level of the tunable resistive device by one unit conductance value in response to the weight update control signal, wherein the one unit conductance value corresponds to one unit weight value of the RPU device.

公开(公告)号：GB2559915B

公开(公告)日：2020-02-19

申请号：GB201807583

申请日：2016-09-19

Applicant: IBM

Inventor： TAYFUN GOKMEN ,  YURII VLASOV ,  SEYOUNG KIM

IPC: G06N3/063

Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.

公开(公告)号：GB2618232A

公开(公告)日：2023-11-01

申请号：GB202310291

申请日：2021-10-25

Applicant: IBM

Inventor： MALTE JOHANNES RASCH ,  TAYFUN GOKMEN ,  SEYOUNG KIM

IPC: G11C13/00

Abstract: A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RPU cells. Peripheral circuitry comprising readout circuitry is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuitry to perform a first operation and a second operation on the array of RPU cells. The control signals include a first configuration control signal to configure the readout circuitry to have a first hardware configuration when the first operation is performed on the array of RPU cells, and a second configuration control signal to configure the readout circuitry to have a second hardware configuration, which is different from the first hardware configuration, when the second operation is performed on the array of RPU cells.

公开(公告)号：GB2577463A

公开(公告)日：2020-03-25

申请号：GB202000225

申请日：2018-06-14

Applicant: IBM

Inventor： KEVIN WAYNE BREW ,  DENNIS NEWNS ,  TALIA SIMCHA GERSHON ,  TEODOR KRASSIMIROV TODOROV ,  GLENN JOHN MARTYNA ,  SEYOUNG KIM

IPC: H01L45/00

Abstract: Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of a phase separated material disposed on the first inert metal contact, wherein the phase separated material includes interstitial ions; and a second inert metal contact disposed on the layer of the phase separated material. The first phase of the phase separated material can have a different concentration of the interstitial ions from the second phase of the phase separated material such that the first phase of the phase separated material has a different electrical conductivity from the second phase of the phase separated material. A method for operating the present memristive device is also provided.

公开(公告)号：GB2592813A

公开(公告)日：2021-09-08

申请号：GB202106235

申请日：2019-09-30

Applicant: IBM

Inventor： SEYOUNG KIM ,  HYUNGJUN KIM ,  TAYFUN GOKMEN ,  MALTE RASCH

IPC: G06F3/00 ,  G06N3/08 ,  G11C11/00

Abstract: Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array (802, 804) having a set of conductive row wires (806a, 806b) and a set of conductive column wires (808a, 808b) intersecting the set of conductive row wires (806a, 806b), and optimizable crosspoint devices (810a, 810b) at intersections of the set of conductive column wires (808a, 808b) and the set of conductive row wires (806a, 806b). A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices (810a) in the weight array until all of the crosspoint devices (810a) in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint devices (810a) from the weight array to the reference array.

公开(公告)号：GB2585992A

公开(公告)日：2021-01-27

申请号：GB202016348

申请日：2019-04-01

Applicant: IBM

Inventor： SEYOUNG KIM ,  TAYFUN GOKMEN

IPC: G06N3/063 ,  G06N3/08

Abstract: Systems and methods are provided to perform weight update operations in a resistive processing unit (RPU) system to update weight values of RPU devices comprising tunable resistive device. A weight update operation for a given RPU device includes maintaining a weight update accumulation value for the RPU device, adjusting the weight update accumulation value by one unit update value in response to a detected coincidence of stochastic bits streams of input vectors applied on an update row and update column control lines connected to the RPU device, generating a weight update control signal in response to the accumulated weight value reaching a predefined threshold value, and adjusting a conductance level of the tunable resistive device by one unit conductance value in response to the weight update control signal, wherein the one unit conductance value corresponds to one unit weight value of the RPU device.

公开(公告)号：GB2577463B

公开(公告)日：2020-08-19

申请号：GB202000225

申请日：2018-06-14

Applicant: IBM

Inventor： KEVIN WAYNE BREW ,  DENNIS NEWNS ,  TALIA SIMCHA GERSHON ,  TEODOR KRASSIMIROV TODOROV ,  GLENN JOHN MARTYNA ,  SEYOUNG KIM

IPC: H01L45/00

Abstract: Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of a phase separated material disposed on the first inert metal contact, wherein the phase separated material includes interstitial ions; and a second inert metal contact disposed on the layer of the phase separated material. The first phase of the phase separated material can have a different concentration of the interstitial ions from the second phase of the phase separated material such that the first phase of the phase separated material has a different electrical conductivity from the second phase of the phase separated material. A method for operating the present memristive device is also provided.

公开(公告)号：GB2592813B

公开(公告)日：2022-05-11

申请号：GB202106235

申请日：2019-09-30

Applicant: IBM

Inventor： SEYOUNG KIM ,  HYUNGJUN KIM ,  TAYFUN GOKMEN ,  MALTE RASCH

IPC: G06F3/00 ,  G06N3/063 ,  G06N3/08

Abstract: Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array having a set of conductive row wires and a set of conductive column wires intersecting the set of conductive row wires, and optimizable crosspoint devices at intersections of the set of conductive column wires and the set of conductive row wires. A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices in the weight array until all of the crosspoint devices in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint device from the weight array to the reference array.

公开(公告)号：GB2577831B

公开(公告)日：2021-10-13

申请号：GB201918712

申请日：2018-06-01

Applicant: IBM

Inventor： KEVIN WAYNE BREW ,  DENNIS NEWNS ,  SEYOUNG KIM ,  TALIA SIMCHA GERSHON ,  TEODOR KRASSIMIROV TODOROV

IPC: H01L27/12

Abstract: A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.

公开(公告)号：GB2610332B

公开(公告)日：2024-12-04

申请号：GB202216836

申请日：2021-03-01

Applicant: IBM

Inventor： SEYOUNG KIM ,  MINGU KANG ,  KYUHYOUN KIM ,  SEONGHOON WOO

IPC: G11C27/02 ,  G06F7/523 ,  G06N3/06 ,  G06N3/065 ,  H03K19/02 ,  H03M1/66

Abstract: A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.