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    DEVICE FOR SHORTENING THE CYCLE TIME IN A DATA PROCESSING DEVICE
    2.
    发明专利
    DEVICE FOR SHORTENING THE CYCLE TIME IN A DATA PROCESSING DEVICE 未知

    公开(公告)号：DE3166256D1

    公开(公告)日：1984-10-31

    申请号：DE3166256

    申请日：1981-03-23

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： BAZLEN DIETER DR ,  HAJDU JOHANN ,  KNAUFT GUNTER

    IPC: G06F7/00 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G06F7/48 ,  G06F9/38

    Abstract: The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking. A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains. By thus splitting the chain of logic circuits into two partial chains, the logic partial functions can be executed during that time segment which is composed of the above mentioned added time segments.

    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS
    3.
    发明专利
    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS 未知

    公开(公告)号：GB1243160A

    公开(公告)日：1971-08-18

    申请号：GB2225670

    申请日：1970-05-08

    Applicant: IBM

    Inventor： KNAUFT GUNTER ,  KOEDERITZ FRITZ ,  LAMPE HANS HERMANN ,  PAINKE HELMUT ,  REICHL LEOPOLD ,  VACHENAUER ROBERT ,  VOGT EDWIN ,  WEBER HERMANN

    IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42

    Abstract: 1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.

    METHOD AND DEVICE FOR TESTING SEQUENTIAL CIRCUITS REALIZED BY MONOLITHIC INTEGRATED SEMICONDUCTOR CIRCUITS
    4.
    发明专利
    METHOD AND DEVICE FOR TESTING SEQUENTIAL CIRCUITS REALIZED BY MONOLITHIC INTEGRATED SEMICONDUCTOR CIRCUITS 未知

    公开(公告)号：DE2961692D1

    公开(公告)日：1982-02-18

    申请号：DE2961692

    申请日：1979-08-07

    Applicant: IBM

    Inventor： HAJDU JOHANN ,  KNAUFT GUNTER

    IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

    Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

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