公开(公告)号：US3659273A

公开(公告)日：1972-04-25

申请号：US3659273D

申请日：1970-05-26

Applicant: IBM

Inventor： KNAUFT GUNTER ,  KOEDERITZ FRITZ ,  PAINKE HELMUT ,  REICHL LEOPOLD ,  LAMPE HANS H ,  VACHENAUER ROBERT ,  VOGT EDWIN ,  WEBER HERMANN

IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42 ,  G06F3/02 ,  G06F3/04

CPC classification number: G06F11/2221 ,  G06F11/2236 ,  G06F11/2268 ,  G06F11/2294 ,  G06F13/4247

Abstract: This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their functions without interference with the CPU usage of the devices and without shutting down of the system.

Abstract translation: 本公开是用于重新布置小型中央处理单元（CPU）的输入/输出控制，以便CPU和客户工程师能够散布使用输入/输出设备。 此配置允许工程师读取设备的状态并测试其功能，而不会干扰设备的CPU使用情况，而不会关闭系统。

公开(公告)号：DE1927549A1

公开(公告)日：1970-12-03

申请号：DE1927549

申请日：1969-05-30

Applicant: IBM DEUTSCHLAND

Inventor： KNAUFT GUENTER ,  LEOPOLD REICHL DIPL-ING ,  EDWIN VOGT DIPL-ING ,  KOEDERITZ FRITZ ,  PAINKE HELMUT ,  WEBER HERMANN ,  HERMANN LAMPE HANS ,  KACHENAUER ROBERT

IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42 ,  G06F3/02

Abstract: This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their functions without interference with the CPU usage of the devices and without shutting down of the system.

公开(公告)号：GB1243160A

公开(公告)日：1971-08-18

申请号：GB2225670

申请日：1970-05-08

Applicant: IBM

Inventor： KNAUFT GUNTER ,  KOEDERITZ FRITZ ,  LAMPE HANS HERMANN ,  PAINKE HELMUT ,  REICHL LEOPOLD ,  VACHENAUER ROBERT ,  VOGT EDWIN ,  WEBER HERMANN

IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42

Abstract: 1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.