公开(公告)号：DE2610881A1

公开(公告)日：1976-10-07

申请号：DE2610881

申请日：1976-03-16

Applicant: IBM

Inventor： LANE RALPH DAVID ,  MANNING RICHARD ARTHUR

IPC: G11C11/411 ,  G11C15/04

公开(公告)号：DE2302137A1

公开(公告)日：1973-10-04

申请号：DE2302137

申请日：1973-01-17

Applicant: IBM

Inventor： DAVIDSON EVAN EZRA ,  LANE RALPH DAVID ,  SAIA JERRY

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02 ,  G11C7/00

Abstract: 1367058 Capacitive memory cells INTERNATIONAL BUSINESS MACHINES CORP 1 Feb 1973 [20 March 1972] 5028/73 Heading H3T A capacitor data storage cell CS is refreshed during a read operation by a latch circuit 9. Data is read from CS by a F.E.T. Q1 in response to a low voltage on the word line 4. If a high level (1) is stored, a transistor 7 conducts to raise the bit line 5, and this triggers the latch 9 which is an SCR in Fig. 1. The latch acts to raise the voltage on line 5 above that which was necessary to initiate triggering, and this raised voltage is fed through another transistor 6 to refresh the storage cell CS. The capacitance of the line 5 is discharged by a transistor 12 which is turned on at the beginning of a read operation, but turned off before the word line 4 voltage is lowered to effect reading. Transistors 12 and Q1 are turned on together, however, if it is desired to write a "0" (i.e. CS is earthed). To write a "1" a further transistor 13 is turned on to raise bit line 5 to +V while word line 4 turns on Q1. Instead of the SCR 9, an emitter coupled pair (16, 17, Fig. 2, not shown) with a positive feedback emitter follower 20, may be used; this has to be reset by a transistor inverter 25. The collector load in the emitter coupled pair may be either a resistor, or (Fig. 3, not shown) a F.E.T. (31) with a gate-source capacitor which is precharged by a further F.E.T. 29 and which boosts conduction of the load F.E.T. (31). The load F.E.T. (31) is fed with a pulsed power supply which is high during a read (refresh) operation, but goes low thereafter and resets the latch by way of the feedback transistor (30).

公开(公告)号：DE2447350A1

公开(公告)日：1975-04-17

申请号：DE2447350

申请日：1974-10-04

Applicant: IBM

Inventor： HANSEN AAGE ANSGAR ,  LANE RALPH DAVID

IPC: G11C17/00 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C7/06 ,  G11C11/14

Abstract: Disclosed is a high voltage driver circuit for writing information into a read mostly memory array, the memory cells of the array being characterized by requiring much higher potential levels for writing information than for reading information.

公开(公告)号：DE2409472A1

公开(公告)日：1974-09-26

申请号：DE2409472

申请日：1974-02-28

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  BARILE CONRAD ALBERT ,  LANE RALPH DAVID ,  LIU PETER TSUNG-SHIH

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L11/14

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.