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    Inverter circuits utilizing minority carrier injection in a semiconductor deivce
    2.
    发明授权
    Inverter circuits utilizing minority carrier injection in a semiconductor deivce 失效
    逆变器电路在半导体器件中使用少量载流子注入

    公开(公告)号：US3696285A

    公开(公告)日：1972-10-03

    申请号：US3696285D

    申请日：1970-04-14

    Applicant: IBM

    Inventor： SAIA JERRY

    IPC: H02M1/00 ,  H02M1/32 ,  H02M3/338 ,  H03K3/33 ,  H02M7/48

    CPC classification number: H02M1/32 ,  H02M3/338 ,  H03K3/33

    Abstract: A family of circuits characterized by storage mode operation in a switching circuit employs minority carrier injection from the base into the collector region of a semi-conductor device. The minority carrier charge stored in the collector thereafter causes amplified forward collector emitter current when forward collector potential is applied. Particular examples of the circuit family include inverters, single shot circuits, transistor oscillators and electronic switching in general.

    Abstract translation: 在开关电路中以存储模式操作为特征的电路系列使用从基极到半导体器件的集电极区域的少数载流子注入。 此后收集的少数载流子电荷在施加正向集电极电位时会产生放大的正向集电极发射极电流。 电路系列的具体实例包括逆变器，单电路电路，晶体管振荡器和电子开关。

    Timed switch circuits utilizing minority carrier injection in a semiconductor device
    4.
    发明授权
    Timed switch circuits utilizing minority carrier injection in a semiconductor device 失效
    在半导体器件中使用少量载体注入的定时开关电路

    公开(公告)号：US3875432A

    公开(公告)日：1975-04-01

    申请号：US18843071

    申请日：1971-10-21

    Applicant: IBM

    Inventor： SAIA JERRY

    IPC: H02M1/00 ,  H02M1/32 ,  H02M3/338 ,  H03K3/33 ,  H03K3/26 ,  H03K19/08

    CPC classification number: H02M1/32 ,  H02M3/338 ,  H03K3/33

    Abstract: A family of circuits characterized by storage mode operation in a switching circuit employs minority carrier injection from the base into the collector region of a semi-conductor device. The minority carrier charge stored in the collector thereafter causes amplified forward collector emitter current when forward collector potential is applied. Particular examples of the circuit family includes inverters, single shot circuits transistor oscillators and electronic switching in general.

    Abstract translation: 在开关电路中以存储模式操作为特征的电路系列使用从基极到半导体器件的集电极区域的少数载流子注入。 此后收集的少数载流子电荷在施加正向集电极电位时会产生放大的正向集电极发射极电流。 电路系列的具体实例包括逆变器，单次电路晶体管振荡器和电子开关。

    6.
    发明专利
    未知

    公开(公告)号：DE1562118A1

    公开(公告)日：1970-02-19

    申请号：DE1562118

    申请日：1968-01-10

    Applicant: IBM

    Inventor： SAIA JERRY ,  LEROY SPENCER DARYL

    IPC: H04M3/02 ,  H04M19/02 ,  H04B5/00

    Abstract: 1,142,982. Automatic exchange systems. INTERNATIONAL BUSINESS MACHINES CORP. 10 Jan., 1968 [13 Jan., 1967], No. 1372/68. Heading H4K. In a ringing circuit for substations having a line transformer T with equal primary windings P2, P2, the ringing current is directed in parallel through the said windings so that no noise passes across the transformer to the switching equipment. To initiate ringing, a signal at terminal 42 is amplified to turn on a controlled rectifier D1 allowing current to flow from an A.C. source 12 to the ringing equipment 8 and thence to P1, P2. Transistor Q1 is turned on to bring the lower end of P1 to substantially ground potential. D5, D2 serve to discharge the ring capacitor during non-ringing periods. In the off-hook condition, the flow of D.C. turns on Q2 which turns off D1 to inhibit further ringing. At the same time an indication is given at terminal 41 through a dial integrator. The circuit is usefully employed in exchanges provided with solid state switching equipment.

    LATCH TYPE REGENERATIVE CIRCUIT FOR READING A DYNAMIC MEMORY CELL
    7.
    发明专利
    LATCH TYPE REGENERATIVE CIRCUIT FOR READING A DYNAMIC MEMORY CELL 未知

    公开(公告)号：CA981365A

    公开(公告)日：1976-01-06

    申请号：CA163470

    申请日：1973-02-08

    Applicant: IBM

    Inventor： DAVIDSON EVAN E ,  LANE RALPH D ,  SAIA JERRY

    IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02

    Abstract: 1367058 Capacitive memory cells INTERNATIONAL BUSINESS MACHINES CORP 1 Feb 1973 [20 March 1972] 5028/73 Heading H3T A capacitor data storage cell CS is refreshed during a read operation by a latch circuit 9. Data is read from CS by a F.E.T. Q1 in response to a low voltage on the word line 4. If a high level (1) is stored, a transistor 7 conducts to raise the bit line 5, and this triggers the latch 9 which is an SCR in Fig. 1. The latch acts to raise the voltage on line 5 above that which was necessary to initiate triggering, and this raised voltage is fed through another transistor 6 to refresh the storage cell CS. The capacitance of the line 5 is discharged by a transistor 12 which is turned on at the beginning of a read operation, but turned off before the word line 4 voltage is lowered to effect reading. Transistors 12 and Q1 are turned on together, however, if it is desired to write a "0" (i.e. CS is earthed). To write a "1" a further transistor 13 is turned on to raise bit line 5 to +V while word line 4 turns on Q1. Instead of the SCR 9, an emitter coupled pair (16, 17, Fig. 2, not shown) with a positive feedback emitter follower 20, may be used; this has to be reset by a transistor inverter 25. The collector load in the emitter coupled pair may be either a resistor, or (Fig. 3, not shown) a F.E.T. (31) with a gate-source capacitor which is precharged by a further F.E.T. 29 and which boosts conduction of the load F.E.T. (31). The load F.E.T. (31) is fed with a pulsed power supply which is high during a read (refresh) operation, but goes low thereafter and resets the latch by way of the feedback transistor (30).

    8.
    发明专利
    未知

    公开(公告)号：DE1912456A1

    公开(公告)日：1970-02-19

    申请号：DE1912456

    申请日：1969-03-12

    Applicant: IBM

    Inventor： SWARTZLANDER HOFFMANN JUN HARR ,  SAIA JERRY

    IPC: G05F3/22 ,  H03F1/30 ,  H03F1/32 ,  H03F3/18 ,  H03F3/195 ,  H03F3/343 ,  H03F3/347 ,  H03H11/40 ,  H03F1/34

    Abstract: 1,256,736. Transistor circuits. INTERNATIONAL BUSINESS MACHINES CORP. 12 March, 1969 [15 March, 1968], No. 12907/69. Heading H3T. [Also in Division G3] The collector of each transistor 10, 12, Fig. 2, of a complementary pair is connected to the base of the other transistor and is also connected to a respective diode 15, 17, to form a three terminal network 22, 23, 25 (or 21, 24, 25, Fig. 3, not shown). The diodes may be the functions of further transistors (Figs. 1b, 1c, not shown) and each transistor 10, 12 may be replaced by a complementary pair (Fig. 1a, not shown) in which the collector of one is joined to the emitter of the other, and the base of the one to the collector of the other. Circuits employing this three terminal network are: (a) An impedance converter (Fig. 4, not shown) in which a voltage is applied (at 25) and the impedance between a terminal (22) and ground is negative and proportional to the impedance Z R between another terminal (23) and ground; (b) A voltage regulator (Fig. 5, not shown) in which a voltage is applied (at 25), a reference voltage (at 23), a start-up diode (33) is connected in the reverse direction across diode (15) and a diode (37) is connected between the output terminals (22) and 23 for overvoltage protection, the voltage across a load R1 connected at 22 being regulated. In an alternative regulator (Fig. 8, not shown) two complete networks as in Fig. 2 are connected in cascade. If I 0 rises due to a fall in load impedance R1, then the positive feedback of the circuit further increases I 0 to keep V 0 unchanged; (c) A current generator (Fig. 6, not shown) in which the current through the common terminal (25) is regulated by a reference voltage applied (at 23) through an impedance R5, the terminal (22) being grounded; (d) A differential amplifier (Fig. 7, not shown) in which a voltage is applied through impedance Rb to one terminal (25) while the voltages to be compared are applied to another terminal (at 22) and through an impedance Z r (at 23), the output Vb appearing (at 25).

    GEOMETRIC CURRENT AMPLIFIER
    9.
    发明专利
    GEOMETRIC CURRENT AMPLIFIER 未知

    公开(公告)号：CA942855A

    公开(公告)日：1974-02-26

    申请号：CA45252

    申请日：1969-03-11

    Applicant: IBM

    Inventor： HOFFMAN HARRY S JR ,  SAIA JERRY

    IPC: G05F3/22 ,  H03F1/30 ,  H03F1/32 ,  H03F3/18 ,  H03F3/195 ,  H03F3/343 ,  H03F3/347 ,  H03H11/40

    Abstract: 1,256,736. Transistor circuits. INTERNATIONAL BUSINESS MACHINES CORP. 12 March, 1969 [15 March, 1968], No. 12907/69. Heading H3T. [Also in Division G3] The collector of each transistor 10, 12, Fig. 2, of a complementary pair is connected to the base of the other transistor and is also connected to a respective diode 15, 17, to form a three terminal network 22, 23, 25 (or 21, 24, 25, Fig. 3, not shown). The diodes may be the functions of further transistors (Figs. 1b, 1c, not shown) and each transistor 10, 12 may be replaced by a complementary pair (Fig. 1a, not shown) in which the collector of one is joined to the emitter of the other, and the base of the one to the collector of the other. Circuits employing this three terminal network are: (a) An impedance converter (Fig. 4, not shown) in which a voltage is applied (at 25) and the impedance between a terminal (22) and ground is negative and proportional to the impedance Z R between another terminal (23) and ground; (b) A voltage regulator (Fig. 5, not shown) in which a voltage is applied (at 25), a reference voltage (at 23), a start-up diode (33) is connected in the reverse direction across diode (15) and a diode (37) is connected between the output terminals (22) and 23 for overvoltage protection, the voltage across a load R1 connected at 22 being regulated. In an alternative regulator (Fig. 8, not shown) two complete networks as in Fig. 2 are connected in cascade. If I 0 rises due to a fall in load impedance R1, then the positive feedback of the circuit further increases I 0 to keep V 0 unchanged; (c) A current generator (Fig. 6, not shown) in which the current through the common terminal (25) is regulated by a reference voltage applied (at 23) through an impedance R5, the terminal (22) being grounded; (d) A differential amplifier (Fig. 7, not shown) in which a voltage is applied through impedance Rb to one terminal (25) while the voltages to be compared are applied to another terminal (at 22) and through an impedance Z r (at 23), the output Vb appearing (at 25).

    10.
    发明专利
    未知

    公开(公告)号：DE2302137A1

    公开(公告)日：1973-10-04

    申请号：DE2302137

    申请日：1973-01-17

    Applicant: IBM

    Inventor： DAVIDSON EVAN EZRA ,  LANE RALPH DAVID ,  SAIA JERRY

    IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02 ,  G11C7/00

    Abstract: 1367058 Capacitive memory cells INTERNATIONAL BUSINESS MACHINES CORP 1 Feb 1973 [20 March 1972] 5028/73 Heading H3T A capacitor data storage cell CS is refreshed during a read operation by a latch circuit 9. Data is read from CS by a F.E.T. Q1 in response to a low voltage on the word line 4. If a high level (1) is stored, a transistor 7 conducts to raise the bit line 5, and this triggers the latch 9 which is an SCR in Fig. 1. The latch acts to raise the voltage on line 5 above that which was necessary to initiate triggering, and this raised voltage is fed through another transistor 6 to refresh the storage cell CS. The capacitance of the line 5 is discharged by a transistor 12 which is turned on at the beginning of a read operation, but turned off before the word line 4 voltage is lowered to effect reading. Transistors 12 and Q1 are turned on together, however, if it is desired to write a "0" (i.e. CS is earthed). To write a "1" a further transistor 13 is turned on to raise bit line 5 to +V while word line 4 turns on Q1. Instead of the SCR 9, an emitter coupled pair (16, 17, Fig. 2, not shown) with a positive feedback emitter follower 20, may be used; this has to be reset by a transistor inverter 25. The collector load in the emitter coupled pair may be either a resistor, or (Fig. 3, not shown) a F.E.T. (31) with a gate-source capacitor which is precharged by a further F.E.T. 29 and which boosts conduction of the load F.E.T. (31). The load F.E.T. (31) is fed with a pulsed power supply which is high during a read (refresh) operation, but goes low thereafter and resets the latch by way of the feedback transistor (30).

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