公开(公告)号：DE2611158A1

公开(公告)日：1976-10-28

申请号：DE2611158

申请日：1976-03-17

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES ,  POPONIAK MICHAEL ROBERT

IPC: H01L21/306 ,  H01L21/3063 ,  H01L21/308 ,  B28D5/06

Abstract: 1515031 Electrolytic etching of silicon INTERNATIONAL BUSINESS MACHINES CORP 3 Feb 1976 [14 April 1975] 4111/76 Heading C7B [Also in Division H1] A hole is made in a monocrystalline silicon body by providing masking with aligned apertures on parallel opposed faces of the body, providing a conductor in contact with the body through one of the openings and using this as anode in an anodic treatment to convert the entire region between the apertures to porous silicon which is then etched out to leave a hole. Typically a plurality of holes are simultaneously formed in a 100 oriented wafer which may have integrated circuitry formed on one or both faces. The masking may consist of silicon dioxide or nitride with an optical overlayer of chromium, or of silicon oxynitride or nitride-onoxide. After photoetching to form the apertures heavily doped surface regions may be formed below the apertures on one or both faces by impurity diffusion or implantation of helium ions or protons and a chromium anode layer deposited on one face. After anodic treatment in a 1:2 mixture of 49% hydrofluoric acid and distilled water the anode is removed and the porous silicon etched out.

公开(公告)号：DE2409472A1

公开(公告)日：1974-09-26

申请号：DE2409472

申请日：1974-02-28

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  BARILE CONRAD ALBERT ,  LANE RALPH DAVID ,  LIU PETER TSUNG-SHIH

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L11/14

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

公开(公告)号：DE3174802D1

公开(公告)日：1986-07-17

申请号：DE3174802

申请日：1981-06-23

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  MAGDO INGRID EMESE

IPC: H01L21/822 ,  H01L21/033 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H01L29/73 ,  H03K19/09 ,  H01L21/82 ,  H01L21/60

Abstract: The method supplies self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I L) or Merged Transistor Logic (MTL) technology. The insulation between the contacts and the metal is a pattern of dielectric material (24, 26, 30) having a thickness dimension in the order of a micron or less. … The method involves providing a silicon body (10, 12) and then forming a first insulating layer (16) on the silicon body. This layer is removed in areas designated to contain integrated injection logic devices. A layer (20) of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer (20) by reactive ion etching which results in the structure having substantially horizontal and vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer (24, 26, 30) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer (24, 26, 30) substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the silicon body. The base of the lateral injector transistor is formed through the openings of the polycrystalline silicon layer (20). The structure is annealed to fully form the base of the transistor and to drive into the silicon body the opposite type impurities from the polycrystalline silicon layer (20) to thereby form the base regions for the vertical transistors of the integrated injection logic circuit. Additional openings and narrow dimensioned dielectric patterns are made in the polycrystalline silicon layer where the collector of the vertical transistor is to be formed. Finally the structure is contacted and planarized.

公开(公告)号：DE2744059A1

公开(公告)日：1978-04-13

申请号：DE2744059

申请日：1977-09-30

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/76 ,  H01L29/72

公开(公告)号：DE2657511A1

公开(公告)日：1977-07-07

申请号：DE2657511

申请日：1976-12-18

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  ANANTHA NARASIPUR GUNDAPPA ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  G11C11/36 ,  G11C16/04 ,  H01L27/07 ,  H01L27/102 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/872 ,  H01L29/94 ,  G11C11/34

Abstract: 1503300 Semiconductor memory device INTERNATIONAL BUSINESS MACHINES CORP 16 Nov 1976 [31 Dec 1975] 47660/76 Heading H1K A semiconductor memory device comprises an electrode 18, Fig. 2, forming a Schottkybarrier contact with an epitaxial layer 13 of one conductivity type, the electrode overlying a region 14 of second conductivity type formed in a surface region of a substrate 11 of said one conductivity type, and an insulating layer 21, 22 around the Schottky-barrier contact overlain by a conductive layer 24 which is insulated from the said electrode, the arrangement being such that when a predetermined voltage is applied across the Schottky barrier, the electrons produced in the avalanche breakdown of the Schottky diode are trapped in the insulating layer. During the above mentioned write operation, the conductive layer 24, typically of doped polysilicon is held at a high positive potential as compared to the electrode 18 and the terminals 30, 33 are at zero potential. During a non-destructive read operation, a substantial current flows from the electrode 18 to the P + diffusion 14 because of the trapped charges forming a depletion region 45 in the epitaxial layer. The insulating layer typically comprises silicon oxide and silicon nitride sublayers and the polysilicon layer 24 is separated from the electrode 18 by a silicon dioxide layer 26. Electrical connection to the P+ region 14 is achieved through a P+ diffused zone and a metal electrode (not shown), whereas the electrical contact 33 is made either at the bottom of the substrate or at the top of the epitaxial layer through an N + diffused region. A member matrix comprising the memory devices formed at the cross-overs of metallized tracks (31a, 31b), and the P+ diffused zones (14a, 14b), Fig. 1 (not shown) is disclosed

公开(公告)号：DE2644832A1

公开(公告)日：1977-06-02

申请号：DE2644832

申请日：1976-10-05

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/283 ,  H01L21/28 ,  H01L21/314 ,  H01L21/76 ,  H01L21/8247 ,  H01L29/41 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/04

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

公开(公告)号：DE2318912A1

公开(公告)日：1974-01-17

申请号：DE2318912

申请日：1973-04-14

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  CHANG CHI SHIH ,  FREEMAN JUN LEO BOYES ,  KNEPPER RONALD WILLIAM

IPC: H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/06 ,  H01L19/00

公开(公告)号：DE2235801A1

公开(公告)日：1973-03-22

申请号：DE2235801

申请日：1972-07-21

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  STERN PAUL GEORGE

IPC: G11C17/06 ,  G11C11/30 ,  G11C16/02 ,  G11C17/14 ,  H01L23/525 ,  G11C17/00

Abstract: An electronically rewritable read-only memory comprising an integrated semiconductor array of P-N junctions formed in a semiconductor substrate. A dielectric film is formed on the surface of the substrate on top of which a thin metallic film is deposited. The dielectric is thinner above an active region of each of the junctions than it is above the other regions of the substrate. When a suitable voltage is applied across the metallic film and dielectric, the metallic film diffuses through the dielectric film at the thinner areas, thereby forming ohmic via connections with the active junction regions. At the same time, the dielectric "self-heals" i.e., the via connections are disconnected from the metallic film around the periphery of the thin areas of the dielectric. A second layer of metallization over the metallic film establishes conductive contact between the layer and the active junction region. The contacts can be broken at selected junctions by passing a current through the diffused metallization. The contacts can be reestablished at selected junctions by applying a suitable healing voltage across the metallic film and the dielectric.

公开(公告)号：DE3278597D1

公开(公告)日：1988-07-07

申请号：DE3278597

申请日：1982-12-27

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  MAGDO INGRID EMESE

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/336 ,  H01L21/768 ,  H01L23/485 ,  H01L29/73 ,  H01L29/78 ,  H01L21/60 ,  H01L23/48

Abstract: A process is described which achieves self-aligned contacts and electrodes (42, 44, 46) having very close spacing in integrated circuit devices by use of a pattern of dielectric material (30) having a thickness in the order of a micrometer or less. A pattern of recessed oxide isolation (32) between device areas in the substrate (10) is also self-aligned by this process. The result is a substantial planar integrated circuit structure. The process is applicable to either bipolar transistor integrated circuits or MOS field effect transistor integrated circuits.

公开(公告)号：DE3175618D1

公开(公告)日：1987-01-02

申请号：DE3175618

申请日：1981-06-23

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  MAGDO INGRID EMESE

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/41 ,  H01L21/31 ,  H01L21/00

Abstract: A method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.