公开(公告)号：DE69526006T2

公开(公告)日：2003-01-02

申请号：DE69526006

申请日：1995-07-13

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  LARY JENIFER EDITH ,  SPROGIS EDMUND JURIS

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

公开(公告)号：DE69526006D1

公开(公告)日：2002-05-02

申请号：DE69526006

申请日：1995-07-13

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  LARY JENIFER EDITH ,  SPROGIS EDMUND JURIS

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.