公开(公告)号：JP2010153812A

公开(公告)日：2010-07-08

申请号：JP2009258033

申请日：2009-11-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KRYWANCZYK TIMOTHY C ,  SPROGIS EDMUND JURIS ,  CODDING STEVEN ROSS ,  TIMOTHY E NEARY

IPC: H01L21/304 ,  B23K26/36 ,  H01L21/301

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/27436 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a method of thinning a semiconductor substrate and a structures for effecting the same. SOLUTION: A C4 (controlled collapse chip connection) grind tape and a laser-ablative adhesive layer are formed on the front surface of a semiconductor substrate. Then, a carrier substrate is mounted to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, and the carrier substrate provides mechanical support in order to thin the semiconductor substrate to the thickness of about 25 μm during a thinning procedure. A film-frame tape is mounted on the back side of the thinned semiconductor substrate, the laser-ablative adhesive layer is polished by laser beam, and thereby the carrier substrate is separated from the back side of the C4 grind tape. An assembly comprising the film-frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. An ultraviolet beam is irradiated to the C4 grind tape, causing degradation in its adhesiveness. Thereafter, the C4 grind tape is removed. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使半导体衬底变薄的方法和用于实现其的结构。 解决方案：在半导体衬底的前表面上形成C4（可控制的崩溃芯片连接）研磨带和激光烧蚀粘合剂层。 然后，将载体基板安装到激光烧蚀粘合剂层。 通过研磨或研磨使半导体衬底的背面变薄，并且在稀化过程中，载体衬底提供机械支撑以便将半导体衬底薄化至约25μm的厚度。 在薄型半导体衬底的背侧安装胶卷胶带​​，通过激光束对激光烧蚀粘合剂层进行抛光，从而使载体衬底与C4磨带的背面分离。 将包括薄膜框架带，变薄的半导体衬底和C4研磨带的组件切块。 紫外线照射到C4研磨胶带，导致其粘合性降低。 此后，除去C4研磨带。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010251754A

公开(公告)日：2010-11-04

申请号：JP2010091384

申请日：2010-04-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAUBENSPECK TIMOTHY HARRISON ,  SULLIVAN TIMOTHY DOOLING ,  WRIGHT STEVEN LORENZ ,  SAUTER WOLFGANG ,  SPROGIS EDMUND JURIS

IPC: H01L21/3205 ,  H01L21/60 ,  H01L23/52

CPC classification number: H01L24/03 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PROBLEM TO BE SOLVED: To provide a metal wiring structure for a uniform current density in a C4 ball. SOLUTION: A sub-pad assembly of a metal structure is arranged directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure that comes into contact with the metal pad and a set of metal vias that provide electrical connection between the upper level metal line structure and a lower level metal line structure arranged underneath of the upper level metal line structure. The reliability of a C4 ball is improved by using a metal pad structure having a set of integrated metal vias that are divided and distributed to promote an uniform current density distribution in the C4 ball. The areal density of the cross-sectional area of the plurality of metal vias is higher at the center part of the metal pad than at the peripheral edge part of the flat part of the metal pad. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在C4球中具有均匀电流密度的金属布线结构。

解决方案：金属结构的子焊盘组件直接布置在金属焊盘下方。 子焊盘组件包括与金属焊盘接触的上层金属线结构和一组金属通孔，其在上层金属线结构和布置在上层下方的下层金属线结构之间提供电连接 金属线结构。 通过使用具有一组集成金属通孔的金属焊盘结构，C4球的可靠性得到改善，该金属焊盘结构被分割和分配以促进C4球中均匀的电流密度分布。 金属焊盘的中心部分的金属通孔的横截面积的面密度比在金属焊盘的平坦部分的周缘部分高。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：DE69526006T2

公开(公告)日：2003-01-02

申请号：DE69526006

申请日：1995-07-13

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  LARY JENIFER EDITH ,  SPROGIS EDMUND JURIS

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

公开(公告)号：DE3884040T2

公开(公告)日：1994-04-14

申请号：DE3884040

申请日：1988-04-08

Applicant: IBM

Inventor： SPROGIS EDMUND JURIS

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  G11C29/24

Abstract: A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.

公开(公告)号：DE69526006D1

公开(公告)日：2002-05-02

申请号：DE69526006

申请日：1995-07-13

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  LARY JENIFER EDITH ,  SPROGIS EDMUND JURIS

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

公开(公告)号：DE3884040D1

公开(公告)日：1993-10-21

申请号：DE3884040

申请日：1988-04-08

Applicant: IBM

Inventor： SPROGIS EDMUND JURIS

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  G11C29/24

Abstract: A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.