公开(公告)号：GB2514709A

公开(公告)日：2014-12-03

申请号：GB201415474

申请日：2013-02-19

Applicant: IBM

Inventor： SLEIGHT JEFFERY W ,  CHANG JOSEPHINE B ,  LAUER ISSAC ,  NARASIMHA SHREESH

IPC: H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire 18" suspended above a semiconductor oxide layer (26) that is present on a first portion (100) of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region (20A) and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region (20B). The first and second pad regions are located above and are in direct contact with a second portion (102) of the bulk semiconductor substrate which is vertically offsets from the first portion (100). The structure further includes a gate (27) surrounding a central portion (18C) of the at least one semiconductor nanowire, a source region (40, 50A) located on a first side of the gate, and a drain region (40', 50B) located on a second side of the gate which is opposite the first side of the gate.