公开(公告)号：EP1875516A4

公开(公告)日：2008-08-13

申请号：EP06739771

申请日：2006-03-27

Applicant: IBM

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L21/8244 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。 体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。 阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：EP2409332A4

公开(公告)日：2012-01-25

申请号：EP10753837

申请日：2010-02-11

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FREEMAN GREGORY G ,  MCSTAY KEVIN ,  NARASIMHA SHREESH

IPC: H01L29/739 ,  H01L21/285 ,  H01L21/329 ,  H01L21/33 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

公开(公告)号：JP2010004006A

公开(公告)日：2010-01-07

申请号：JP2008259405

申请日：2008-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

IPC: H01L29/786

CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of an semiconductor-on-insulator device by providing the semiconductor-on-insulator device with a body contact. SOLUTION: In one embodiment, the invention provides a semiconductor device that includes: a substrate including a semiconductor layer positioned overlaying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present around a perimeter of the semiconducting body; a gate structure overlaying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过提供绝缘体上半导体器件与体接触来减小绝缘体上半导体器件的寄生电容。 解决方案：在一个实施例中，本发明提供了一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体本体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2005094006A

公开(公告)日：2005-04-07

申请号：JP2004266302

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  NARASIMHA SHREESH

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L27/12

CPC classification number: H01L21/2022 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide an improving method of the quality of a defective semiconductor crystal in the vicinity of the surface thereof.
SOLUTION: A method where amorphization step and subsequent thermal treatment step are executed on the defective semiconductor crystal material is provided. In the amorphization step, a region including the surface area of the defective semiconductor crystal material is partially or completely amorphized. Next, the thermal treatment step is executed to recrystallize the amorphized area of the defective semiconductor crystal material. Recrystallization is achieved, by re-growing the solid phase crystal from the amorphized area of the defective semiconductor crystal material.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在其表面附近的缺陷半导体晶体的质量的改进方法。 解决方案：提供了对缺陷半导体晶体材料执行非晶化步骤和随后的热处理步骤的方法。 在非晶化步骤中，包含缺陷半导体晶体材料的表面积的区域部分或完全非晶化。 接下来，进行热处理步骤，使缺陷半导体晶体材料的非晶化区域重结晶。 通过从有缺陷的半导体晶体材料的非晶化区域重新生长固相晶体来实现重结晶。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006113061A2

公开(公告)日：2006-10-26

申请号：PCT/US2006011167

申请日：2006-03-27

Applicant: IBM ,  CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L29/94

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种包括具有SOI区域和体硅区域的衬底的6T-SRAM半导体结构，其中SOI区域和体硅区域具有相同或不同的晶体取向; 将SOI区域与本体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层的顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：WO2011043870A3

公开(公告)日：2011-06-23

申请号：PCT/US2010046567

申请日：2010-08-25

Applicant: IBM ,  LI YING ,  NARASIMHA SHREESH ,  RAUSCH WERNER A

Inventor： LI YING ,  NARASIMHA SHREESH ,  RAUSCH WERNER A

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/78615 ,  H01L21/74 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66772

Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

Abstract translation: 公开了具有FET区域，体接触区域和STI区域的体硅层上的SOI器件。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。 身体接触区域包括SOI层的延伸部，延伸部上的第​​二STI层和与延伸部接触的身体接触部。 第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

公开(公告)号：JP2005317980A

公开(公告)日：2005-11-10

申请号：JP2005131468

申请日：2005-04-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ASHIMA B CHAKRAVARTI ,  NARASIMHA SHREESH ,  CHAN VICTOR ,  JUDSON HOLT ,  SATYA N CHAKRAVARTI

IPC: H01L21/768 ,  C23C16/34 ,  H01L21/318 ,  H01L21/469 ,  H01L29/78

CPC classification number: H01L29/7843 ,  C23C16/345 ,  H01L21/3185

Abstract: PROBLEM TO BE SOLVED: To provide a material that can exhibit a desirable stress in using a field effect transistor, e.g., sufficiently high stress for an etching stop liner (e.g., a stress that exceeds +10G dyne/cm
2 , stress of approximately +14.5G dyne/cm
2 in a preferred embodiment), and further continues to exhibit the desirable high stress after repeated annealing.
SOLUTION: Stress level of a nitride film is adjusted as two or more functions of the following: (1) selection of a starting material precursor to be used to make the nitride film, by use of which the starting material precursor is processed, (2) selection of a precursor including nitrogen, (3) the ratio of the starting material precursor and the precursor including nitrogen, (4) a set of CVD conditions for growing the film and (5) a thickness that grows the film. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound including silicon, nitrogen and carbon (e.g., bis-t-butylaminosilane (BTBAS)) with NH
3 can provide an advantageous characteristic such as performance excellent in high use or an etching stop application. An ammonia treated BTBAS film is especially excellent in providing a high-stress characteristic and is capable of maintaining the high-stress characteristic even if annealing is repeated.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在使用场效应晶体管时可以表现出期望的应力的材料，例如用于蚀刻停止衬垫的足够高的应力（例如，超过+ 10G达因/ cm 2的应力< 2 ，在优选实施例中约为+ 14.5G达因/厘米2 / SP>的应力），并且在反复退火之后还继续表现出期望的高应力。 解决方案：将氮化膜的应力水平调整为以下两个或更多个功能：（1）选择用于制造氮化物膜的起始材料前体，通过使用原料前体进行处理 ，（2）包括氮的前体的选择，（3）原料前体和前体的比例包括氮的比例，（4）用于生长膜的一组CVD条件和（5）使膜生长的厚度。 通过使包含硅，氮和碳的化合物（例如，双 - 叔丁基氨基硅烷（BTBAS））与NH 3 SBB反应生成的快速热化学气相沉积（RTCVD）膜可以提供有利的特性，例如 性能优异的高使用或蚀刻停止应用。 氨处理的BTBAS膜在提供高应力特性方面特别优异，并且即使重复退火也能够保持高应力特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2007133394A

公开(公告)日：2007-05-31

申请号：JP2006294934

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CULP JAMES A ,  LARS W LIEBMAN ,  MALIK RAJEEV ,  MULLER K PAUL ,  NARASIMHA SHREESH ,  RUNYON STEPHEN L ,  WILLIAMS PATRICK M

IPC: G03F1/08 ,  H01L21/82

CPC classification number: G06F17/5068

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving the yield, performance and timing of an integrated circuit. SOLUTION: An iterative timing analysis is performed analytically before a chip is fabricated, based on a technique that uses optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time-sensitive devices. An additional mask is used as a selective trim, to form shortened gate lengths or wider metal lines for selected predetermined transistors, affecting threshold voltages and RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. This analysis methodology is repeated as often as needed, to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants, until manufacturing limits are reached. A mask is made for the selected critical devices by using OPC techniques. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于提高集成电路的产量，性能和时序的方法。 解决方案：基于使用光学邻近校正技术缩短栅极长度和调整关键时间敏感器件的金属线宽度和接近距离的技术，在芯片制造之前分析地执行迭代时序分析。 使用附加掩模作为选择性修整，以形成选定的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 该分析方法根据需要经常重复，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为选定的关键设备制作掩码。 版权所有（C）2007，JPO＆INPIT