公开(公告)号：EP2522027A4

公开(公告)日：2014-05-28

申请号：EP11732060

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG HSUN ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78612 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66772

Abstract: In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.

公开(公告)号：EP2519976A4

公开(公告)日：2014-02-19

申请号：EP11735025

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

公开(公告)号：EP2522032A4

公开(公告)日：2014-05-28

申请号：EP11732064

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

公开(公告)号：EP2396812A4

公开(公告)日：2012-08-01

申请号：EP10767544

申请日：2010-04-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  MO RENEE T ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66795

公开(公告)号：JP2010272859A

公开(公告)日：2010-12-02

申请号：JP2010108180

申请日：2010-05-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG JOSEPHINE B ,  GUILLORN MICHAEL A ,  SLEIGHT JEFFREY W ,  CHANG PAUL

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a nanowire mesh of a single gate inverter and a method of fabricating the same. SOLUTION: The field effect transistor (FET) includes a plurality of device layers disposed vertically in a stack, each device layer has a source region, a drain region and a plurality of nanowire channels 110 connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant or a p-type dopant. The FET inverter further includes a common gate 150 surrounding the plurality of nanowire channels, a first contact 156 to the source regions of the one or more device layers doped with the n-type dopant, a second contact 158 to the source regions of the one or more device layers doped with the p-type dopant, and a common third contact 152 to the drain regions of each of the device layers. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供单栅极逆变器的纳米线网及其制造方法。 解决方案：场效应晶体管（FET）包括在堆叠中垂直设置的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道110 其中一个或多个器件层的源区和漏区掺杂有n型掺杂剂或p型掺杂剂。 FET反相器还包括围绕多个纳米线通道的公共栅极150，向掺杂有n型掺杂剂的一个或多个器件层的源极区域提供的第一接触156，一个或多个纳米线通道的源极区域的第二接触158 或更多的掺杂有p型掺杂剂的器件层，以及与每个器件层的漏极区域的公共第三接触152。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011082519A

公开(公告)日：2011-04-21

申请号：JP2010226294

申请日：2010-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIN CHUNG-HSUN ,  BEDELL STEPHEN W ,  CHANG JOSEPHINE B

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L29/66477 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit having silicon on a stress liner, and its manufacturing method. SOLUTION: The method comprises a step of preparing a semiconductor substrate comprising an outer semiconductor layer and an embedded sacrifice layer under the outer semiconductor layer, and a step of removing at least a portion of the embedded sacrifice layer to form a void within the semiconductor substrate. The method further comprises a step of depositing a material in the void to form the stress liner, and a step of forming a transistor on the outer semiconductor layer of the semiconductor substrate. The outer semiconductor layer separates the transistor from the stress liner. The semiconductor substrate includes isolation regions, and the removing step includes a step of forming recesses in the isolation regions, and a step of removing at least a portion of the embedded sacrifice layer via these recesses. The depositing step includes a step of depositing a material in the void via the recesses 46. End caps 60 are formed in the recesses 46 contacting with ends of the stress liner. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在应力衬垫上具有硅的集成电路及其制造方法。 解决方案：该方法包括制备半导体衬底的步骤，该半导体衬底包括在外部半导体层下面的外部半导体层和嵌入的牺牲层，以及去除至少一部分嵌入的牺牲层以在其中形成空隙的步骤 半导体衬底。 该方法还包括在空隙中沉积材料以形成应力衬垫的步骤，以及在半导体衬底的外半导体层上形成晶体管的步骤。 外半导体层将晶体管与应力衬垫分开。 半导体衬底包括隔离区域，并且去除步骤包括在隔离区域中形成凹部的步骤，以及通过这些凹部去除嵌入的牺牲层的至少一部分的步骤。 沉积步骤包括通过凹部46将材料沉积在空隙中的步骤。在与应力衬垫的端部接触的凹部46中形成端盖60。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2012047770A3

公开(公告)日：2012-06-21

申请号：PCT/US2011054521

申请日：2011-10-03

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

Inventor： CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract translation: 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。

公开(公告)号：WO2013052935A1

公开(公告)日：2013-04-11

申请号：PCT/US2012059152

申请日：2012-10-06

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHANG LELAND ,  ENGELMANN SEBASTIAN U ,  GUILLORN MICHAEL A

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  ENGELMANN SEBASTIAN U ,  GUILLORN MICHAEL A

IPC: H01L29/66

CPC classification number: B81C1/0023 ,  B81B2207/015 ,  B81C1/00801 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/565 ,  H01L21/845 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract translation: 用于制造在基板上分离机电装置和CMOS装置的阻挡层的结构和方法。 示例性结构包括封装机电装置的保护层，其中阻挡层可以承受能够去除保护层而不是阻挡层的蚀刻工艺。 衬底可以是绝缘体上硅或多层晶片衬底。 机电装置可以是微机电系统（MEMS）或纳米机电系统（NEMS）。

公开(公告)号：WO2011090907A3

公开(公告)日：2012-03-08

申请号：PCT/US2011021326

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L21/8232 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/772

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. Sn one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer, In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Abstract translation: 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。在另一个实施例中，在氧阻隔层上存在低电阻率金属层。

公开(公告)号：WO2011084975A3

公开(公告)日：2011-12-29

申请号：PCT/US2011020173

申请日：2011-01-05

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

Abstract translation: 在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。 在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。