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公开(公告)号：DE3785211T2
公开(公告)日：1993-10-07
申请号：DE3785211
申请日：1987-10-30
Applicant: IBM
Inventor： CALVIGNAC JEAN , DAUPHIN MICHEL , LENOIR RAYMOND , PICARD JEAN-LOUIS
Abstract: A process for updating the frame check sequence FCSr(x) of a digital frame including an embedded variable header polynomial Hr(x), said process including : XORing the modified polynomial header Ht(x) and previous polynomial header Hr(x) to generate a differential polynomial D(x); computing a differential frame check polynomial sequence dFCS (x) on said D(x) and adding dFCS(x) to the polynomial FCSr(x).
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公开(公告)号：DE3786404T2
公开(公告)日：1994-01-20
申请号：DE3786404
申请日：1987-11-27
Applicant: IBM
Inventor： CALVIGNAC JEAN , LENOIR RAYMOND , DAUPHIN MICHEL , PICARD JEAN-LOUIS
Abstract: A data handling system wherein data are arranged into frames including an information data section and a frame check sequence (FCS) section, and wherein a stamp section has to be appended/deleted from said frame. The stamp appending is operated without any FCS updating being required by appending to each stamp, a so called precomputed and stored anti-stamp.
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公开(公告)号：DE3786404D1
公开(公告)日：1993-08-05
申请号：DE3786404
申请日：1987-11-27
Applicant: IBM
Inventor： CALVIGNAC JEAN , LENOIR RAYMOND , DAUPHIN MICHEL , PICARD JEAN-LOUIS
Abstract: The system includes a device for generating an antistamp section made to neutralise the contribution of the stamp section to FCS, a device for appending anti-stamp section to the stamp section so that a tag is generated and a device for appending tag to data section. The FCS is the remainder of the division of a polynomial representation of data section by a predetermined generating polynomial G(X). A stamp storage is used for storing a so called stamp representing the TDM slot reference corresponding to each HDLC frame. An anti-stamp storage serves for storing predetermined stamp dependant anti-stamp data.
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公开(公告)号：DE3785211D1
公开(公告)日：1993-05-06
申请号：DE3785211
申请日：1987-10-30
Applicant: IBM
Inventor： CALVIGNAC JEAN , DAUPHIN MICHEL , LENOIR RAYMOND , PICARD JEAN-LOUIS
Abstract: The entire frame (Mr(x)) as received is serialised under clock control at bit rate which also governs serialisation of the new header (Ht(x)) extracted from a buffer register. The serialisers' outputs are gated by a HEADER GATE signal and its inverse. An Exclusive-OR operation is applied to the modified and previous polynomial headers in order to generate the difference polynomial (D(x)) on which a differential frame check polynomial sequence (dFCS) is computed for modulo-2 addn. to the original frame check sequence. The sum iss inserted in the SDLC frame at the proper location.
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