公开(公告)号：DE3275694D1

公开(公告)日：1987-04-16

申请号：DE3275694

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： PICARD JEAN-LOUIS

IPC: H04L25/38 ,  H04L7/00 ,  H04L23/02 ,  H04L25/48 ,  H04L25/49 ,  H04L29/00 ,  G08C19/28

Abstract: A data transmission system wherein data are entered upon activation of input points of an entry unit (1) of the keyboard type, including a sequence generation unit (5) generating a series of "maximum length" sequences on to a series-output (8) and a different binary pattern for each bit in the sequence on to a parallel-output (6). Such a binary pattern is compared in a coincidence circuit (7) with the binary representation of an activated point of the entry unit (1) so as to produce a bit "one" on line (9) which alters, through an X OR circuit (10), the corresponding bit in the sequence to be transmitted over the transmission line (11).

公开(公告)号：DE3785211T2

公开(公告)日：1993-10-07

申请号：DE3785211

申请日：1987-10-30

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  DAUPHIN MICHEL ,  LENOIR RAYMOND ,  PICARD JEAN-LOUIS

IPC: H03M13/00 ,  H03M13/09 ,  H04L1/00

Abstract: A process for updating the frame check sequence FCSr(x) of a digital frame including an embedded variable header polynomial Hr(x), said process including : XORing the modified polynomial header Ht(x) and previous polynomial header Hr(x) to generate a differential polynomial D(x); computing a differential frame check polynomial sequence dFCS (x) on said D(x) and adding dFCS(x) to the polynomial FCSr(x).

公开(公告)号：DE2512541A1

公开(公告)日：1975-10-30

申请号：DE2512541

申请日：1975-03-21

Applicant: IBM

Inventor： CALLENS PAUL ,  PICARD JEAN-LOUIS ,  POULET ALAIN

IPC: H04L29/08 ,  H04J3/07 ,  H04J3/08 ,  H04L13/08 ,  H04L25/30 ,  H04L25/38

公开(公告)号：DE1244861B

公开(公告)日：1967-07-20

申请号：DEC0026929

申请日：1962-05-07

Applicant: IBM FRANCE

Inventor： PICARD JEAN-LOUIS

IPC: G01S7/28 ,  G06F5/06 ,  G06F7/50 ,  G06F7/505 ,  G06F13/00 ,  G06F17/40 ,  H03M1/00

公开(公告)号：DE3786404T2

公开(公告)日：1994-01-20

申请号：DE3786404

申请日：1987-11-27

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LENOIR RAYMOND ,  DAUPHIN MICHEL ,  PICARD JEAN-LOUIS

IPC: H03M13/09 ,  H04L1/00 ,  H03M13/00

Abstract: A data handling system wherein data are arranged into frames including an information data section and a frame check sequence (FCS) section, and wherein a stamp section has to be appended/deleted from said frame. The stamp appending is operated without any FCS updating being required by appending to each stamp, a so called precomputed and stored anti-stamp.

公开(公告)号：DE3786404D1

公开(公告)日：1993-08-05

申请号：DE3786404

申请日：1987-11-27

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LENOIR RAYMOND ,  DAUPHIN MICHEL ,  PICARD JEAN-LOUIS

IPC: H03M13/09 ,  H04L1/00 ,  H03M13/00

Abstract: The system includes a device for generating an antistamp section made to neutralise the contribution of the stamp section to FCS, a device for appending anti-stamp section to the stamp section so that a tag is generated and a device for appending tag to data section. The FCS is the remainder of the division of a polynomial representation of data section by a predetermined generating polynomial G(X). A stamp storage is used for storing a so called stamp representing the TDM slot reference corresponding to each HDLC frame. An anti-stamp storage serves for storing predetermined stamp dependant anti-stamp data.

公开(公告)号：DE3785211D1

公开(公告)日：1993-05-06

申请号：DE3785211

申请日：1987-10-30

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  DAUPHIN MICHEL ,  LENOIR RAYMOND ,  PICARD JEAN-LOUIS

IPC: H03M13/00 ,  H03M13/09 ,  H04L1/00

Abstract: The entire frame (Mr(x)) as received is serialised under clock control at bit rate which also governs serialisation of the new header (Ht(x)) extracted from a buffer register. The serialisers' outputs are gated by a HEADER GATE signal and its inverse. An Exclusive-OR operation is applied to the modified and previous polynomial headers in order to generate the difference polynomial (D(x)) on which a differential frame check polynomial sequence (dFCS) is computed for modulo-2 addn. to the original frame check sequence. The sum iss inserted in the SDLC frame at the proper location.

公开(公告)号：DE3679068D1

公开(公告)日：1991-06-06

申请号：DE3679068

申请日：1986-06-25

Applicant: IBM

Inventor： PICARD JEAN-LOUIS

IPC: H04L12/56 ,  H04L29/00 ,  H04L12/54 ,  G06F15/16

Abstract: The invention relates to a method of routing data blocks in a data communication network comprising a plurality of nodes through which the data blocks are routed. A node identifier and a port identifier are assigned to each node and to each port in the nodes,respectively. Once the route has been established in the sending station, thereby identifying the nodes in the route to be crossed over by the data blocks and in each node of the route the destination port to be used by that node, the sending station includes in the data blocks to be sent a routing tag RT whose value is such that: RT modulo (Ni) = Pi where Ni are the node identifiers of the nodes in the route, and Pi are the destination port identifiers of the respective nodes in the route. At each node receiving a data block, dividing RT by the node identifier provides the the destination port identifier which specifies the port through which the received block has to be retransmitted.