公开(公告)号：US3748647A

公开(公告)日：1973-07-24

申请号：US3748647D

申请日：1971-06-30

Applicant: IBM

Inventor： ASHANY R ,  LINDQUIST A

IPC: G06F13/42 ,  G06F15/173 ,  G06F15/16

CPC classification number: G06F15/17337 ,  G06F13/4213

Abstract: Units of a data processing system intercommunicate on ring connections of shift registers. A message placed in one shift register stage is advanced from stage to stage until it is removed at a destination stage or at an intermediate stage. Several rings are interconnected in a toroidal arrangement so that a message can be transferred at an intermediate stage from one ring to an adjacent ring. Logic is provided for advantageously routing the message between the initial stage and the destination stage.

Abstract translation: 数据处理系统的单元在移位寄存器的环形连接上相互通信。 放置在一个移位寄存器阶段的消息从一个阶段提前到另一个阶段，直到在目标阶段或中间阶段被移除。 几个环以环形布置互连，使得消息可以在中间阶段从一个环转移到相邻的环。 逻辑被提供用于在初始阶段和目的地阶段之间有利地路由消息。

公开(公告)号：SE371312B

公开(公告)日：1974-11-11

申请号：SE705072

申请日：1972-05-30

Applicant: IBM

Inventor： ASHANY R ,  LINDQUIST A

IPC: G06F13/42 ,  G06F15/173 ,  G06F15/16

公开(公告)号：SE348580B

公开(公告)日：1972-09-04

申请号：SE40768

申请日：1968-01-12

Applicant: IBM

Inventor： LINDQUIST A ,  PRICER W ,  SEEBER R

IPC: G11C15/04 ,  G11C15/00

Abstract: 1,188,666. Associative stores; read-only stores. INTERNATIONAL BUSINESS MACHINES CORP. 15 Dec., 1967 [13 Jan., 1967], No. 57023/67. Headings G4A and G4C. Each word in a matrix associative memory has a unique address field. Each word in the transistorized memory has an erasable data field and a read-only address field, the address fields specifying the word locations and thus being all different. An input register has a data field and an address field, and by masking off one of them an associative search may be done on the data fields or the address fields, the matching word or words being read out to an output register. The output register also receives an indication of the number of matches (0, 1 or a plurality) provided by logic fed by the output of the address fields since in the case of more than one match at least one address bit position will be indicated as being both 1 and 0 (on separate lines) and in the case of no match any particular bit will not be indicated as being either.

公开(公告)号：SE309431B

公开(公告)日：1969-03-24

申请号：SE1265861

申请日：1961-12-19

Applicant: IBM

Inventor： LINDQUIST A

IPC: G11C15/06 ,  G11C11/44

Abstract: 972, 862. Cryotron stores; associative memories. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 6, 1961 [Dec. 22, 1960], No. 43640/61. Heading G4C. [Also in Division H3] An associative memory employs as storage elements persistent current cryotrons in which the value of a binary digit is indicated by the direction of flow of the current about a closed superconductive loop. An associative operation is in two stages. In the first the memory is scanned for the wanted word and in the second, requiring actuation of switches, a read or write operation takes place. Storage matrix (Fig. 2). Words occupy rows of the matrix and like order bits the columns. To write a ''1" in the top left-hand storage cell of the matrix shown positive current is applied to line 32 and any current to write line 151. Thin film cryotron 195 sends section 125a, 125d resistive and current flows in the loop 125a, 125b, 125d. The write current is stopped and then that on line 32. The current in the loop flows over the section 125d, 125a to form a closed circuit of clockwise circulating persistent current. To write a "0", the same process is followed with a negative current on line 32. The result is a counterclockwise circulation of the persistent current in the loop. The switch 51 (Fig. 3) is used to control read-in and read-out to the first column of the matrix and is shown set to read-in "0" when gates 74a, 74e, 74c, and 7 are sent resistive by current from source 71 to steer negative current from terminal 41 over line 32 to terminal 4. Non-destructive read-out of the storage cell is done by steering current from terminal 91 to either terminal 101, representing "0", or terminal 102, representing "1". Switch 51 is set to contacts 81a, 81b. Gates 74c, 74d, 74e, 67a and 67b are sent resistive. Positive current is applied to terminal 21 and any current to read line 154 (Fig. 2). A reset line 180 (Fig. 3) is pulsed. Current from terminal 21 is steered to line 31 and about the comparison loop 121. Cryotron 191 is of a kind which, if the currents in the two associated parallel conductors are flowing in the same direction becomes resistive. If the cell is storing "1" this is the case. Loop 121 becomes resistive and current from line 31 is steered to branch 164 where it sends gate 111 b resistive, so that current from terminal 91 is steered to terminal 102. Associative operations. The switch 66 (Fig.4) is set to line 107. The required digits are set on the switches 51 to 53 unless it is not desired to interrogate a particular column when the switch, 51 say, is set at "mask" contacts 174a, 174b. This diverts currents from terminals 21 or 41 directly to earth. The value of the tag being searched is entered in the same way as a write operation but instead of energizing the write line such as 151, the current is applied to the compare lines 161 to 163 (Fig. 2). If the values of a tag bit and a storage bit are the same the algebraic sum of currents flowing in section 125a, 125d of the storage loop is zero. If the values differ the current in this section is sufficient to send cryotron 188, hitherto unaffected by the persistent current, resistive. Current from "equal" line 161 is steered to "notequal" line 171. In Fig. 4 it can be seen that current from terminal 26a is steered to terminal 25a on line 27a if an equal comparison has been made in the first row of the matrix, on line 28a otherwise. One of these conditions having been established switch 66 is set to contact 108 and switch 65 to the operation required. By this means the current on the "equal" line of the row at which an equal comparison has been made is steered to the read or write line 151 or 154 say, of that register, so that read or write follows automatically on the switches 51 to 53 having been set. Some modifications of the basic storage cell are described (Figs. 8 and 11, not shown) which use instead of cryotrons such as 191, dual cryotrons having two control windings. The Specification points out that the not-equal lines give signals representing an exclusive-or function and the equal lines the complement of this. Specification 968,544 is referred to.