System for determining line measure
    3.
    发明授权
    System for determining line measure 失效
    用于确定线路测量的系统

    公开(公告)号:US3647041A

    公开(公告)日:1972-03-07

    申请号:US3647041D

    申请日:1970-06-30

    Applicant: IBM

    CPC classification number: B41J19/64

    Abstract: A system for determining and entering line measure into a justification computer for controlling the format of output copy. During an output operation when there is a necessity for determining line measure, a measure seek code is detected, escapement of the carrier initiated, the escapement of the carrier sensed, and the units of escapement counted. Upon sensing the location of the right margin stop, escapement is terminated. Thereafter the carrier is returned to the position occupied prior to the measure seek code being read. The number of units counted is the line measure which is then used for control of output.

    Abstract translation: 一种用于确定和输入线性度量的系统,用于控制输出副本的格式。 在需要确定线路测量的输出操作期间,检测出测量寻道码,启动的载波的擒纵机构,感测到的载波的擒纵机构和擒纵机构的数量。 一旦感测到右边缘挡块的位置,擒纵机构终止。 此后,载波返回到被读取的测量寻找代码之前被占用的位置。 计算的单位数是用于控制输出的线测量。

    7.
    发明专利
    未知

    公开(公告)号:FR2316699A1

    公开(公告)日:1977-01-28

    申请号:FR7611976

    申请日:1976-04-16

    Applicant: IBM

    Abstract: 1526474 Testing and repairing magnetic bubble chips INTERNATIONAL BUSINESS MACHINES CORP 26 April 1976 [30 June 1975] 16807/76 Addition to 1482998 Heading H3B In a modification of Specification 1,482,998, a series of magnetic bubble register loops is tested and repaired by propagating a chain of scout bubbles through the loops, detecting the chain to sense the occurrence of bubble voids indicative of defective loops, and loading the complementary sensed pattern into repair stations S (one at each loop) to cause the defective loop(s) to be bypassed A. Bubbles loaded onto discs D are replaced by the scout chain via pulsed conductor 22, propagate through the store and are magnetoresistively sensed, after which the complementary scout pattern replaces the original chain which is then destroyed.

    8.
    发明专利
    未知

    公开(公告)号:FR2354596A1

    公开(公告)日:1978-01-06

    申请号:FR7713452

    申请日:1977-04-26

    Applicant: IBM

    Abstract: Logic circuitry is provided for controlling the transfer of data between 1) a low cost pipelined processor and its associated memory, 2) between the processor and input/output devices, and 3) between the input/output devices and memory. A plurality of unidirectional busses are provided to interface the processor and memory and a bidirectional buss is provided to interface with the input/output devices. The logic circuitry provides a control function to steer data over the proper buss structures interconnecting the processor, the memory and the input/output devices and provides those interconnections in a manner which allows the processor to overlap input and output functions.

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