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公开(公告)号：DE3851488T2
公开(公告)日：1995-03-30
申请号：DE3851488
申请日：1988-06-16
Applicant: IBM
Inventor： LIPTAY JOHN STEPHEN
IPC: G06F9/38 , G06F9/46 , G06F9/48 , G11C11/419
Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.
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公开(公告)号：DE2855106A1
公开(公告)日：1979-07-05
申请号：DE2855106
申请日：1978-12-20
Applicant: IBM
Inventor： HUGHES JEFFREY FRANCIS , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER , STONE STANLEY EDWARD
Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.
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公开(公告)号：DE69130858T2
公开(公告)日：1999-10-07
申请号：DE69130858
申请日：1991-11-06
Applicant: IBM
Inventor： COMFORT STEVEN TYLER , LIPTAY JOHN STEPHEN , WEBB CHARLES FRANKLIN
IPC: G06F9/38
Abstract: A system and method whereby a central processor can continue operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system and method, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that the interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and all of the processing was done in a single instant at the moment that the fetches became allowed.
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公开(公告)号：DE2909987A1
公开(公告)日：1979-09-20
申请号：DE2909987
申请日：1979-03-14
Applicant: IBM
Inventor： GANNON PATRICK MELVIN , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER
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Patent Agency Ranking
公开(公告)号：AU4306379A
公开(公告)日：1979-07-12
申请号：AU4306379
申请日：1979-01-02
Applicant: IBM
Inventor： HUGHES JEFFREY FRANCIS , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER , STONE STANLEY EDWARD
Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.
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公开(公告)号：DE69130858D1
公开(公告)日：1999-03-18
申请号：DE69130858
申请日：1991-11-06
Applicant: IBM
Inventor： COMFORT STEVEN TYLER , LIPTAY JOHN STEPHEN , WEBB CHARLES FRANKLIN
IPC: G06F9/38
Abstract: A system and method whereby a central processor can continue operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system and method, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that the interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and all of the processing was done in a single instant at the moment that the fetches became allowed.
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公开(公告)号：DE3851488D1
公开(公告)日：1994-10-20
申请号：DE3851488
申请日：1988-06-16
Applicant: IBM
Inventor： LIPTAY JOHN STEPHEN
IPC: G06F9/38 , G06F9/46 , G06F9/48 , G11C11/419
Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.
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公开(公告)号：BR8803228A
公开(公告)日：1989-02-08
申请号：BR8803228
申请日：1988-06-30
Applicant: IBM
Inventor： LIPTAY JOHN STEPHEN
IPC: G06F9/38 , G06F9/46 , G06F9/48 , G11C11/419 , G06F15/20
Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.
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