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Patent Agency Ranking
公开(公告)号：DE69021710T2
公开(公告)日：1996-04-18
申请号：DE69021710
申请日：1990-10-31
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BROTMAN CHARLES H , RYMARCZYK JAMES WALTER
Abstract: A large number of processing elements (604) (e.g. 4096) are interconnected by means of a high bandwidth switch (606). Each processing element (604) includes one or more general purpose microprocessors (1202), a local memory (1210) and a DMA controller (1206) that sends and receives messages through the switch (606) without requiring processor intervention. The switch (606) that connects the processing elements is hierarchical and comprises a network of clusters. Sixtyfour processing elements (604) can be combined to form a cluster and and sixtyfour clusters can be linked by way of a Banyan network. Messages are routed through the switch (606) in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch (606) reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element (604), the processing element (604) corrects the error and retransmits the packet through the switch (606) over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.
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公开(公告)号：DE2855106A1
公开(公告)日：1979-07-05
申请号：DE2855106
申请日：1978-12-20
Applicant: IBM
Inventor： HUGHES JEFFREY FRANCIS , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER , STONE STANLEY EDWARD
Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.
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公开(公告)号：DE69021710D1
公开(公告)日：1995-09-21
申请号：DE69021710
申请日：1990-10-31
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BROTMAN CHARLES H , RYMARCZYK JAMES WALTER
Abstract: A large number of processing elements (604) (e.g. 4096) are interconnected by means of a high bandwidth switch (606). Each processing element (604) includes one or more general purpose microprocessors (1202), a local memory (1210) and a DMA controller (1206) that sends and receives messages through the switch (606) without requiring processor intervention. The switch (606) that connects the processing elements is hierarchical and comprises a network of clusters. Sixtyfour processing elements (604) can be combined to form a cluster and and sixtyfour clusters can be linked by way of a Banyan network. Messages are routed through the switch (606) in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch (606) reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element (604), the processing element (604) corrects the error and retransmits the packet through the switch (606) over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.
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公开(公告)号：DE2909987A1
公开(公告)日：1979-09-20
申请号：DE2909987
申请日：1979-03-14
Applicant: IBM
Inventor： GANNON PATRICK MELVIN , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER
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公开(公告)号：AU4306379A
公开(公告)日：1979-07-12
申请号：AU4306379
申请日：1979-01-02
Applicant: IBM
Inventor： HUGHES JEFFREY FRANCIS , LIPTAY JOHN STEPHEN , RYMARCZYK JAMES WALTER , STONE STANLEY EDWARD
Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.
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