公开(公告)号：AU4306379A

公开(公告)日：1979-07-12

申请号：AU4306379

申请日：1979-01-02

Applicant: IBM

Inventor： HUGHES JEFFREY FRANCIS ,  LIPTAY JOHN STEPHEN ,  RYMARCZYK JAMES WALTER ,  STONE STANLEY EDWARD

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/18

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.

公开(公告)号：DE2855106A1

公开(公告)日：1979-07-05

申请号：DE2855106

申请日：1978-12-20

Applicant: IBM

Inventor： HUGHES JEFFREY FRANCIS ,  LIPTAY JOHN STEPHEN ,  RYMARCZYK JAMES WALTER ,  STONE STANLEY EDWARD

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/19

Abstract: In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions, some of which may be conditionally executed. A number of stored pointers identify particular ones of the multiple instruction buffers. Various branch instructions are predicted to be successful or unsuccessful. Result signals from the instruction execution unit, in response to execution of conditional branch instructions, will control the setting of various pointers and busy triggers associated with each instruction buffer, causing the next sequential instruction transferred to the instruction execution unit to be from the proper instruction stream based on the result of the branch on condition instruction.