公开(公告)号：JPS6353785A

公开(公告)日：1988-03-08

申请号：JP9551587

申请日：1987-04-20

Applicant: IBM

Inventor： HELWIG KLAUS ,  LOHLEIN WOLFDIETER ,  TONG MINH H

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

公开(公告)号：DE3685654D1

公开(公告)日：1992-07-16

申请号：DE3685654

申请日：1986-08-22

Applicant: IBM

Inventor： HELWIG KLAUS ,  LOHLEIN WOLFDIETER ,  TONG MINH H

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: Externally generated addresses are fed simultaneously to the two decoders of a memory and to a comparator which also receives fuse addresses, corresponding to redundant word and/or bit lines. In the event of a match signal between external and fuse addresses the redundant word line is activated and all unselected word or bit lines are held. A restore operation for the address decoder is then initiated by switching on the addressing clock. The unselected word or bit lines are held in this condition by a clamp signal which deactivates the address decorder and initiates a restore operation. For a read operation the word or bit line potential is prevented from dropping to earth potential by early disconnection of the selected word or bit line.

公开(公告)号：IT1149978B

公开(公告)日：1986-12-10

申请号：IT2271780

申请日：1980-06-11

Applicant: IBM

Inventor： BSCHWENDTNER JORG ,  LOHLEIN WOLFDIETER

IPC: H03K5/00 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

Abstract: A known FET driver circuit which is to be controlled at the gate by means of relatively low TTL signals, is improved in such a manner that the source potential of the input transistors is shifted oppositely to the input signal. This leads to an increase in the effective potential difference in the signal level applied to the input transistors and thus to an improved switching speed.

公开(公告)号：DE3064023D1

公开(公告)日：1983-08-11

申请号：DE3064023

申请日：1980-06-18

Applicant: IBM

Inventor： GSCHWENDTNER JORG ,  LOHLEIN WOLFDIETER

IPC: H03K5/00 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

Abstract: A known FET driver circuit which is to be controlled at the gate by means of relatively low TTL signals, is improved in such a manner that the source potential of the input transistors is shifted oppositely to the input signal. This leads to an increase in the effective potential difference in the signal level applied to the input transistors and thus to an improved switching speed.