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    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME
    2.
    发明专利
    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME 未知

    公开(公告)号：HK1026064A1

    公开(公告)日：2000-12-01

    申请号：HK00105169

    申请日：2000-08-17

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

    IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

    Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

    SOI PASS-GATE DISTURB SOLUTION
    3.
    发明专利
    SOI PASS-GATE DISTURB SOLUTION 未知

    公开(公告)号：MY124337A

    公开(公告)日：2006-06-30

    申请号：MYPI9903693

    申请日：1999-08-27

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  TONG MINH H

    IPC: H01L21/335 ,  H01L27/01 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10

    Abstract: AN SOI PASS-GATE DISTURB SOLUTION FOR AN N-TYPE MOSFET (30) WHEREIN A RESISTOR (70) IS CONNECTED BETWEEN THE GATE (60) AND THE BODY (40) OF THE FET TO ELIMINATE THE DISTRUB CONDITION . THE FET (100) IS FABRICATED INA SUBSTRATE HAVING A SOURCE (211), A DRAIN (212) AND A GATE (112), WHEREIN THE BODY (108) OF THE FIELD EFFECT TRANSISTOR IS ELECTRICALLY FLOATING AND THE TRANSISTOR IS SUBSTANTIALLY ELECTRICALLY ISOLATED FROM THE SUBSTRATE. A HIGH RESISTANCE PATH (119) IS PROVIDED COUPLING THE ELECTRICALLY FLOATING BODY OF THE FET TO THE GATE, SUCH THAT THE BODY DISCHARGES TO A LOW STATE BEFORE SIGNIFICANT THERMAL CHARGING CAN OCCUR WHEN THE GATE IS LOW, AND THUS PREVENTS THE ACCUMULATION OF A CHARGE ON THE BODY WHEN THE TRANSISTOR IS OFF. THE RESISTANCE OF THE HIGH RESISTANCE PATH IS PREFERABLY APPROXIMATELY 10(10) OHMS-UM DIVIDED BY THE WIDTH OF THE PASS-GATE.FIGURE 2

    5.
    发明专利
    未知

    公开(公告)号：DE3685654D1

    公开(公告)日：1992-07-16

    申请号：DE3685654

    申请日：1986-08-22

    Applicant: IBM

    Inventor： HELWIG KLAUS ,  LOHLEIN WOLFDIETER ,  TONG MINH H

    IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: Externally generated addresses are fed simultaneously to the two decoders of a memory and to a comparator which also receives fuse addresses, corresponding to redundant word and/or bit lines. In the event of a match signal between external and fuse addresses the redundant word line is activated and all unselected word or bit lines are held. A restore operation for the address decoder is then initiated by switching on the addressing clock. The unselected word or bit lines are held in this condition by a clamp signal which deactivates the address decorder and initiates a restore operation. For a read operation the word or bit line potential is prevented from dropping to earth potential by early disconnection of the selected word or bit line.

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