METHOD AND PROGRAM FOR PROCESSING MULTIPLE-REGISTER INSTRUCTION

    公开(公告)号:JPH10228376A

    公开(公告)日:1998-08-25

    申请号:JP34310697

    申请日:1997-12-12

    Applicant: IBM MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To enable access to registers and to effective execute a multiple- register instruction by dispatching an instruction that specifies data words written registers. SOLUTION: A sequencer device 17 stores data in registers GPR 22 and FPR 25 and take the data out of them. A branching device 11 receives a branch instruction and a signal indicating the current state of a processor 10 from the sequencer device 17. The branching device 11 responds to those branch instruction and signal and outputs a signal indicating a proper memory address to the sequencer device 17. The sequencer device 17 once receiving those signals from the branching device 11 takes a series of indicated instructions out of an instruction cache 27. Then the sequencer device 17 dispatches the instructions fetched from the instruction cache 27 selectively to selected execution devices among 11 to 16. Each execution device executes instructions of specific classes.

    PROCESSOR AND METHOD FOR SPECULATIVELY EXECUTING CONDITION BRANCHING COMMAND BY USING SELECTED ONE OF PLURAL BRANCH PREDICTION SYSTEM

    公开(公告)号:JPH10133873A

    公开(公告)日:1998-05-22

    申请号:JP10612897

    申请日:1997-04-23

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide an improved processor and method for speculatively executing a condition branching command by using selected one of plural branch prediction systems. SOLUTION: The processor and the method for speculatively executing a branch command using a selected branch prediction system is disclosed. The processor has one or plural executing units for executing a command which includes a branch processing unit 18 for executing a branch command. In the branch processing unit 18, a selective logic mechanism 66 for selecting one of plural branch prediction systems, and a branch predicting unit for predicting a solution of a conditional branch command using the selected branch prediction system are included. In the branch processing unit 18, an executing function for speculatively executing the conditional branch command based on the prediction is further included. The selective logic mechanism 66 selects a branch prediction system for predicting the following conditional branch command based on the predicted result, and as a result, branch predictive accuracy is improved.

    3.
    发明专利
    未知

    公开(公告)号:DE69719235D1

    公开(公告)日:2003-04-03

    申请号:DE69719235

    申请日:1997-04-25

    Applicant: IBM

    Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

    4.
    发明专利
    未知

    公开(公告)号:DE69719235T2

    公开(公告)日:2003-10-30

    申请号:DE69719235

    申请日:1997-04-25

    Applicant: IBM

    Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

    5.
    发明专利
    未知

    公开(公告)号:AT233414T

    公开(公告)日:2003-03-15

    申请号:AT97302877

    申请日:1997-04-25

    Applicant: IBM

    Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

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