公开(公告)号：DE10002120B4

公开(公告)日：2006-04-20

申请号：DE10002120

申请日：2000-01-20

Applicant: IBM

Inventor： GAERTNER UTE ,  PFEFFER ERWIN ,  SCHELM KERSTIN ,  MACDOUGALL JOHN

IPC: G06F12/1027

Abstract: The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.

公开(公告)号：DE10002120A1

公开(公告)日：2000-11-02

申请号：DE10002120

申请日：2000-01-20

Applicant: IBM

Inventor： GAERTNER UTE ,  PFEFFER ERWIN ,  SCHELM KERSTIN ,  MACDOUGALL JOHN

IPC: G06F12/1027 ,  G06F12/10

Abstract: The buffer storage arrangement has two dividing/partial units (82,84). The first one is a converting buffer (82) for certain higher address converting planes and the second a converting buffer (84) for certain lower address converting planes. The second unit (84) is arranged in such a way that is stores special converting cache (TLB) index address data of the higher unit (82) as a data marker flag in the TLB structure of the lower plane. The first converting buffer (TLB1) is a peak level buffer storage and a second (TLB2) is a second level address converting memory. It is arranged in such a way that it makes available this address data in case of a missing address in the first buffer storage and the second TLB2 is arranged so that it has at least two dividing/partial units (81,82,83,84), and LRU data is provided in both dividing/partial units (81,82,83,84). An Independent claim is also included for A Method for the operation of an address converting buffer arrangement.