公开(公告)号：DE3584657D1

公开(公告)日：1991-12-19

申请号：DE3584657

申请日：1985-07-23

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware dynamic address translation mechanism (DATM) arrangement for generating double-level address translations (i.e. guest virtual/guest absolute = host virtual/host absolute address translations) in combination with a translation look- aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, and without danger of CPU deadlock occurring. The hardware arrangement (DATM) also performs all single-level address translations required by the system.

公开(公告)号：CA1229424A

公开(公告)日：1987-11-17

申请号：CA482002

申请日：1985-05-21

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware arrangement for generating double-level address translations in combination with a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.