公开(公告)号：CA2015214A1

公开(公告)日：1990-11-30

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE TERRENCE K ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17

Abstract: The disclosed arrangement provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High-Speed Channel (HSC) standard on processors complexes like the IBM 3090 having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：CA2015214C

公开(公告)日：1996-01-02

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE DAVID L ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17 ,  G06F13/00

Abstract: This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel interface (HPPI) standard on processors complexes like the IBM? 3090TM having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：DE3584657D1

公开(公告)日：1991-12-19

申请号：DE3584657

申请日：1985-07-23

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware dynamic address translation mechanism (DATM) arrangement for generating double-level address translations (i.e. guest virtual/guest absolute = host virtual/host absolute address translations) in combination with a translation look- aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, and without danger of CPU deadlock occurring. The hardware arrangement (DATM) also performs all single-level address translations required by the system.

公开(公告)号：CA1229424A

公开(公告)日：1987-11-17

申请号：CA482002

申请日：1985-05-21

Applicant: IBM

Inventor： BRANDT HENRY R ,  GANNON PATRICK M ,  LEUNG WAN L ,  MARCHINI TIMOTHY R

IPC: G06F12/10 ,  G06F12/14

Abstract: The disclosure provides a unique high-speed hardware arrangement for generating double-level address translations in combination with a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.