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    OFFSET CORRECTION CIRCUIT OF DIGITAL-ANALOG CONVERTER
    1.
    发明专利
    OFFSET CORRECTION CIRCUIT OF DIGITAL-ANALOG CONVERTER 失效

    公开(公告)号：JPH01122211A

    公开(公告)日：1989-05-15

    申请号：JP20030888

    申请日：1988-08-12

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MARCIANO FREDERIK ,  MICHEL PATRICK

    IPC: H03M1/10 ,  H03M3/02 ,  H04B14/06

    Abstract: PURPOSE: To evade the offset of an analog output by correcting the offset at the time of correcting PLO so that a clock for controlling the input of a digital word to a sigma/delta converter is slowed down or speeded up. CONSTITUTION: A state A is held until the slow-down operation SD or speed-up operation SU of the PLO is executed. When the speed-up operation SU is executed, the system is changed from the state A to a state B at a succeeding crystal oscillator pulse. Then the system is advanced to a state C or a state D in accordance with a result that a sigma/delta bit is a '1' bit or a '0' bit. When the polarity of sigma/delta data is changed, the state is immediately changed from C to E (or D to E). The state E expresses that the generation of a correction pulse is possible. Then the system is returned to the state A waiting for new PLO correction. When the PLO slow-down operation SD is executed, the system directly changed from the state A to the state E for generating a correction pulse.

    2.
    发明专利
    未知

    公开(公告)号：DE3780640D1

    公开(公告)日：1992-08-27

    申请号：DE3780640

    申请日：1987-10-19

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MARCIANO FREDERIK ,  MICHEL PATRICK

    IPC: H03M1/10 ,  H03M3/02 ,  H04B14/06 ,  H03M1/60

    Abstract: The circuit comprises a delta coder (18) providing a serial bit storing at a rate provided by a clock frequency F in response to digital words provided at a frequency f which is lower than F. An analog integrator (22) provides an output signal (24) representing the digital words. In response to an adjust signal which speeds up or slows down f a circuit modifies, by a set duration, the time of one bit from the delta coder. A corrected pulse is produced in place of the sigma-delta data provided by the corrected when modification of that one bit is detected. The corrected pulse lasts half the set duration and introduces an offset which has the same or opposite polarity of the detected bit when the modified bit is lengthened or shortened respectively.

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