中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.015 seconds)

    OFFSET CORRECTION CIRCUIT OF DIGITAL-ANALOG CONVERTER
    1.
    发明专利
    OFFSET CORRECTION CIRCUIT OF DIGITAL-ANALOG CONVERTER 失效

    公开(公告)号：JPH01122211A

    公开(公告)日：1989-05-15

    申请号：JP20030888

    申请日：1988-08-12

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MARCIANO FREDERIK ,  MICHEL PATRICK

    IPC: H03M1/10 ,  H03M3/02 ,  H04B14/06

    Abstract: PURPOSE: To evade the offset of an analog output by correcting the offset at the time of correcting PLO so that a clock for controlling the input of a digital word to a sigma/delta converter is slowed down or speeded up. CONSTITUTION: A state A is held until the slow-down operation SD or speed-up operation SU of the PLO is executed. When the speed-up operation SU is executed, the system is changed from the state A to a state B at a succeeding crystal oscillator pulse. Then the system is advanced to a state C or a state D in accordance with a result that a sigma/delta bit is a '1' bit or a '0' bit. When the polarity of sigma/delta data is changed, the state is immediately changed from C to E (or D to E). The state E expresses that the generation of a correction pulse is possible. Then the system is returned to the state A waiting for new PLO correction. When the PLO slow-down operation SD is executed, the system directly changed from the state A to the state E for generating a correction pulse.

    PHASE-LOCKED CLOCK
    2.
    发明专利
    PHASE-LOCKED CLOCK 未知

    公开(公告)号：DE3374829D1

    公开(公告)日：1988-01-14

    申请号：DE3374829

    申请日：1983-09-07

    Applicant: IBM ,  IBM FRANCE

    Inventor： CUKIER MAURICE

    IPC: H03L7/06 ,  H04J3/06 ,  H04L7/033 ,  H04L7/02

    Abstract: Correction control data on the control lines of a bus (C) indicate whether an internal clock leads or lags behind an external clock. They may also quantify the discrepancy. Digital data is directed to the output of a multiplexer (22) from a chosen decoder. The multiplexer adds or subtracts a predetermined digital value to or from the input value. The data is stored in a flip-flop buffer memory (30) and returned to the input at the rate determined by a fast crystal clock (10). Report logic (32) sends internal clock data via a fixed frequency divider (13) to the phase comparator (20) which receives the external clock signal.

    4.
    发明专利
    未知

    公开(公告)号：DE2825190A1

    公开(公告)日：1979-01-04

    申请号：DE2825190

    申请日：1978-06-08

    Applicant: IBM

    Inventor： CUKIER MAURICE

    IPC: G04G99/00 ,  H03K19/177 ,  G06F7/00

    Abstract: A programmable logic array (PLA) is provided with a plurality of storage registers. The PLA includes an AND matrix which generates inputs to an OR matrix which in turn selectively feeds output signals into the storage registers. At a selected time, a selected storage register provides the output signals of the PLA and/or feedback signals to the AND array so that sequential logic functions can be performed in the PLA. The plurality of storage registers are used to store various combinations of the OR matrix output signals. A decoder permits selection of one of the registers at a time to allow time discrimination among the various stored combinations of the OR matrix output signals for the purposes of feeding them out of the PLA and/or feeding them back into the AND matrix.

    5.
    发明专利
    未知

    公开(公告)号：DE3881883D1

    公开(公告)日：1993-07-22

    申请号：DE3881883

    申请日：1988-08-30

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MAUDUIT DANIEL ,  ORENGO GERARD

    IPC: H03M3/04 ,  H03H17/00 ,  H03H17/06 ,  H04L7/033

    Abstract: The digital filter has clocking in and out frequencies F and submultiple f respectively, the frequency f being synchronised with a remote clock. The ratio F to f determines the number of taps and accumulators (38,40,42) which add the products to tap coefficients and incoming signals (S1,S2,S3) loaded during each clock cycle at frequency F by processing circuit (32,34,36). The accumulators are clocked out sequentially at frequency f and multiplexer (44) selects the next accumulator to be loaded. A zero value tap ensures the last product output is always zero allowing synchronisation. A clock cycle frequency F may be added or skipped. Frequency f is adjusted by a phase locked loop. Both F . and f are generally derived in a single oscillator.

    6.
    发明专利
    未知

    公开(公告)号：DE3780640D1

    公开(公告)日：1992-08-27

    申请号：DE3780640

    申请日：1987-10-19

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MARCIANO FREDERIK ,  MICHEL PATRICK

    IPC: H03M1/10 ,  H03M3/02 ,  H04B14/06 ,  H03M1/60

    Abstract: The circuit comprises a delta coder (18) providing a serial bit storing at a rate provided by a clock frequency F in response to digital words provided at a frequency f which is lower than F. An analog integrator (22) provides an output signal (24) representing the digital words. In response to an adjust signal which speeds up or slows down f a circuit modifies, by a set duration, the time of one bit from the delta coder. A corrected pulse is produced in place of the sigma-delta data provided by the corrected when modification of that one bit is detected. The corrected pulse lasts half the set duration and introduces an offset which has the same or opposite polarity of the detected bit when the modified bit is lengthened or shortened respectively.

    10.
    发明专利
    未知

    公开(公告)号：FR2396468A1

    公开(公告)日：1979-01-26

    申请号：FR7720729

    申请日：1977-06-30

    Applicant: IBM FRANCE

    Inventor： CUKIER MAURICE

    IPC: G04G99/00 ,  H03K19/177 ,  H03K19/08

    Abstract: A programmable logic array (PLA) is provided with a plurality of storage registers. The PLA includes an AND matrix which generates inputs to an OR matrix which in turn selectively feeds output signals into the storage registers. At a selected time, a selected storage register provides the output signals of the PLA and/or feedback signals to the AND array so that sequential logic functions can be performed in the PLA. The plurality of storage registers are used to store various combinations of the OR matrix output signals. A decoder permits selection of one of the registers at a time to allow time discrimination among the various stored combinations of the OR matrix output signals for the purposes of feeding them out of the PLA and/or feeding them back into the AND matrix.

Patent Agency Ranking