公开(公告)号：SG83758A1

公开(公告)日：2001-10-16

申请号：SG1999006260

申请日：1999-12-09

Applicant: IBM

Inventor： MICHAEL J HARGROVE ,  MARIO M PELELLA ,  STEVEN H VOLDMAN

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/822 ,  H01L23/52 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L23/60

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.