公开(公告)号：MY133983A

公开(公告)日：2007-11-30

申请号：MYPI20012657

申请日：2001-06-06

Applicant: IBM

Inventor： JAMES A CULP ,  JAWAHAR P NAYAK ,  WERNER A RAUSCH ,  MELANIE J SHERONY ,  STEVEN H VOLDMAN ,  NOAH D ZAMDMER

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/76 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

Abstract: A SEMICONDUCTOR CHIP INCLUDES A SEMICONDUCTOR SUBSTRATE HAVING A RECTIFYING CONTACT DIFFUSION AND A NON-RECTIFYING CONTACT DIFFUSION. A HALO DIFFUSION IS ADJACENT THE RECTIFYING CONTACT DIFFUSION AND NO HALO DIFFUSION IS ADJACENT THE NON-RECTIFYING CONTACT DIFFUSION. THE RECTIFYING CONTACT DIFFUSION CAN BE A SOURCE/DRAIN DIFFUSION OF AN FET TO IMPROVE RESISTANCE TO PUNCH-THROUGH. THE NON-RECTIFYING CONTACT DIFFUSION MAY BE AN FET BODY CONTACT, A LATERAL DIODE CONTACT, OR A RESISTOR OR CAPACITOR CONTACT. AVOIDING A HALO FOR NON-RECTIFYING CONTACTS REDUCES SERIES RESISTANCE AND IMPROVES DEVICE CHARACTERISTICS. IN ANOTHER EMBODIMENT ON A CHIP HAVING DEVICES WITH HALOS ADJACENT DIFFUSIONS, NO HALO DIFFUSION IS ADJACENT A RECTIFYNG CONTACT DIFFUSION OF A LATERAL DIODE, SIGNIFICANTLY IMPROVING IDEALITY OF THE DIODE AND INCREASING BREAKDOWN VOLTAGE.@@FIGURE 1A

公开(公告)号：SG83758A1

公开(公告)日：2001-10-16

申请号：SG1999006260

申请日：1999-12-09

Applicant: IBM

Inventor： MICHAEL J HARGROVE ,  MARIO M PELELLA ,  STEVEN H VOLDMAN

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/822 ,  H01L23/52 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L23/60

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

公开(公告)号：SG91862A1

公开(公告)日：2002-10-15

申请号：SG200002012

申请日：2000-04-10

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  STEVEN H VOLDMAN ,  RANDY WILLIAM MANN ,  ANDREAS BRYANT ,  ROBERT J GAUTHIER JR

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.