公开(公告)号：EP1805674A4

公开(公告)日：2010-08-04

申请号：EP05808961

申请日：2005-10-14

Applicant: IBM

Inventor： HENG FOOK-LUEN ,  HIBBELER JASON D ,  MCCULLEN KEVIN W ,  NARAYAN RANI R ,  RUNYON STEPHEN L ,  WALKER ROBERT F

IPC: G06F17/50

CPC classification number: G06F17/5068

公开(公告)号：JP2008171406A

公开(公告)日：2008-07-24

申请号：JP2007313627

申请日：2007-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MERVYN YEE-MIN TAN ,  JASON D HIBBELER ,  GUZOWSKI MATTHEW T ,  PAPADOPOULOU EVANTHIA ,  WALKER ROBERT F ,  ALLEN ROBERT J ,  MCCULLEN KEVIN W ,  SARAH C BRAASCH ,  MAYNARD DANIEL N

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5068

Abstract: PROBLEM TO BE SOLVED: To obtain a method, a system and a computer program for providing information for correlating the edges of a layout shape to a critical area of design and defects so that a designer can improve the sensitivity of design to various types of faults.
SOLUTION: The method, the apparatus and the computer program for visually indicating interaction between one or more edges of a design that contribute a pattern of a determined critical area are provided.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了获得用于提供用于将布局形状的边缘与设计和缺陷的关键区域相关联的信息的方法，系统和计算机程序，使得设计者可以将设计的灵敏度提高到各种 故障类型 提供了用于可视地指示有助于确定的关键区域的图案的设计的一个或多个边缘之间的交互的方法，设备和计算机程序。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2006044730A2

公开(公告)日：2006-04-27

申请号：PCT/US2005037145

申请日：2005-10-14

Applicant: IBM ,  HENG FOOK-LUEN ,  HIBBELER JASON D ,  MCCULLEN KEVIN W ,  NARAYAN RANI R ,  RUNYON STEPHEN L ,  WALKER ROBERT F

Inventor： HENG FOOK-LUEN ,  HIBBELER JASON D ,  MCCULLEN KEVIN W ,  NARAYAN RANI R ,  RUNYON STEPHEN L ,  WALKER ROBERT F

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Methods, systems and program products are disclosed for selectively scaling (100) an integrated circuit (IC) design (200): by layer, by unit, or by ground rule, or a combination of these (130). The selective scaling technique can be applied in a feedback loop (408) with the manufacturing system (400) with process and yield feedback (300), during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

Abstract translation: 公开了用于根据层，单元或基础规则或这些的组合（130）选择性地缩放（100）集成电路（IC）设计（200）的方法，系统和程序产品。 选择性缩放技术可以在设计寿命期间与制造系统（400）一起在反馈回路（408）中应用于具有处理和产量反馈（300）的反馈回路（408）中，以提高早期处理中的产量，使得分级结构 保存。 本发明消除了在实现诸如无掩模制造的新技术的情况下涉及设计人员提高产量的需要。