公开(公告)号：DE2319011A1

公开(公告)日：1973-11-15

申请号：DE2319011

申请日：1973-04-14

Applicant: IBM

Inventor： MCMAHON JUN MAURICE THOMAS

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/52 ,  G01R31/02

公开(公告)号：DE2312731A1

公开(公告)日：1973-09-20

申请号：DE2312731

申请日：1973-03-14

Applicant: IBM

Inventor： CARPENTER ROBERT GORDON ,  LINDBLOOM ERIC ,  MCMAHON JUN MAURICE THOMAS

IPC: G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G01R31/28

公开(公告)号：DE2256135A1

公开(公告)日：1973-06-20

申请号：DE2256135

申请日：1972-11-16

Applicant: IBM

Inventor： CARPENTER ROBERT GORDON ,  LINDBLOOM ERIC ,  MCMAHON JUN MAURICE THOMAS

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/22 ,  G01R31/26

Abstract: A system for testing complex circuitry primarily in large scale integration where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a weighted random number generator which applies a test signal to some input terminals of the logic under test more frequently than others. A particular input terminal to the logic under test can be accessed in proportion to the circuit switching activity associated with accessing that particular terminal.

公开(公告)号：DE2349607A1

公开(公告)日：1974-07-04

申请号：DE2349607

申请日：1973-10-03

Applicant: IBM

Inventor： MCMAHON JUN MAURICE THOMAS

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  G01R31/26

Abstract: 1425190 Measuring semi-conductor parameters INTERNATIONAL BUSINESS MACHINES CORP 10 Dec 1973 [29 Dec 1972] 57139/73 Heading G1U In an integrated circuit 12 individual elements 10 are temporarily inter-connected into a test circuit 18, the voltage supplies to the elements are provided and the propagation delay of a signal through the circuit is measured. In the device shown the elements 10 are inverting gates (e.g. NAND or NOR) and an odd number are connected in a loop which oscillates when the power supply is provided. The oscillation half-period is the sum of the individual delays in the gates 10 forming the loop. If the total delay is satisfactory, the temporary inter-connections are broken and the gates connected into the final circuit configuration. The inter-connections may be metal or may be made via photo-sensitive inputs which are sensitized during the test but kept in the dark when the final circuit is formed and used.

公开(公告)号：DE2235802A1

公开(公告)日：1973-02-15

申请号：DE2235802

申请日：1972-07-21

Applicant: IBM

Inventor： MCMAHON JUN MAURICE THOMAS

IPC: G11C29/00 ,  G01R19/165 ,  G01R31/28 ,  G01R31/317 ,  G06F11/22 ,  G06F11/277 ,  G11C29/56 ,  G06F11/10