公开(公告)号：CA949203A

公开(公告)日：1974-06-11

申请号：CA109041

申请日：1971-03-30

Applicant: IBM

Inventor： HEILWEIL MELVIN F ,  MCMAHON MAURICE T JR

IPC: G01R31/3193 ,  G06F11/26 ,  G01R31/28

Abstract: A method and apparatus for testing complex nonlinear binary circuits by applying a bilevel signal pattern, particularly a random pattern, to both a plurality of inputs in the circuit being tested and to a corresponding plurality of inputs in a reference simulation of said circuit, and for comparing corresponding outputs from the circuit and the simulation.

公开(公告)号：CA982230A

公开(公告)日：1976-01-20

申请号：CA184829

申请日：1973-11-01

Applicant: IBM

Inventor： MCMAHON MAURICE T JR

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: 1425190 Measuring semi-conductor parameters INTERNATIONAL BUSINESS MACHINES CORP 10 Dec 1973 [29 Dec 1972] 57139/73 Heading G1U In an integrated circuit 12 individual elements 10 are temporarily inter-connected into a test circuit 18, the voltage supplies to the elements are provided and the propagation delay of a signal through the circuit is measured. In the device shown the elements 10 are inverting gates (e.g. NAND or NOR) and an odd number are connected in a loop which oscillates when the power supply is provided. The oscillation half-period is the sum of the individual delays in the gates 10 forming the loop. If the total delay is satisfactory, the temporary inter-connections are broken and the gates connected into the final circuit configuration. The inter-connections may be metal or may be made via photo-sensitive inputs which are sensitized during the test but kept in the dark when the final circuit is formed and used.

公开(公告)号：CA1000361A

公开(公告)日：1976-11-23

申请号：CA163469

申请日：1973-02-08

Applicant: IBM

Inventor： CARPENTER ROBERT G ,  LINDBLOOM ERIC ,  MCMAHON MAURICE T JR

IPC: G01R31/317 ,  G01R31/3183 ,  G06F11/26

公开(公告)号：CA996268A

公开(公告)日：1976-08-31

申请号：CA158256

申请日：1972-12-05

Applicant: IBM

Inventor： CARPENTER ROBERT G ,  LINDBLOOM ERIC ,  MCMAHON MAURICE T JR

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/22

Abstract: A system for testing complex circuitry primarily in large scale integration where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a weighted random number generator which applies a test signal to some input terminals of the logic under test more frequently than others. A particular input terminal to the logic under test can be accessed in proportion to the circuit switching activity associated with accessing that particular terminal.