公开(公告)号：DE69920830T2

公开(公告)日：2005-10-13

申请号：DE69920830

申请日：1999-06-19

Applicant: IBM

Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.

公开(公告)号：DE69920830D1

公开(公告)日：2004-11-11

申请号：DE69920830

申请日：1999-06-19

Applicant: IBM

Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.