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    DEVICE AND METHOD FOR PERFORMING SHIFT/ROTATE OPERATIONS
    1.
    发明申请
    DEVICE AND METHOD FOR PERFORMING SHIFT/ROTATE OPERATIONS 审中-公开
    用于执行移位/旋转操作的装置和方法

    公开(公告)号：WO2004044731A3

    公开(公告)日：2004-12-16

    申请号：PCT/EP0350754

    申请日：2003-10-24

    Applicant: IBM ,  IBM DEUTSCHLAND ,  BUETTNER STEFAN ,  LEENSTRA JENS ,  MAEDING NICOLAS ,  PILLE JUERGEN

    Inventor： BUETTNER STEFAN ,  LEENSTRA JENS ,  MAEDING NICOLAS ,  PILLE JUERGEN

    IPC: G06F5/01 ,  G06F7/76

    CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F5/015 ,  G06F2207/382 ,  G06F2207/3828

    Abstract: A method and device is provided for performing rotate operations on operands having a size of 2N bits, alternatively, for performing rotate operations on two operands each having a size of N bits to the left, whereby N is an integer. The device includes a control unit being adapted for exchanging M least significant bits of the output of a first rotate circuit with M least significant bits of the output of a second rotate circuit, when M =N is true, whenever an input having the width of 2N is to be rotated by M bits. For rotator arrays rotating N bit wide data to the right, it functions correspondingly.

    Abstract translation: 提供了一种方法和装置，用于对大小为2N位的操作数执行旋转操作，或者用于对两个操作数执行旋转操作，每个操作数具有N位的大小，其中N是整数。 该设备包括控制单元，该控制单元适于在M

    AUTOMATIC CHECK FOR CYCLIC OPERATING CONDITIONS FOR SOI CIRCUIT SIMULATION
    2.
    发明申请
    AUTOMATIC CHECK FOR CYCLIC OPERATING CONDITIONS FOR SOI CIRCUIT SIMULATION 审中-公开
    自动检查用于SOI电路仿真的循环工作条件

    公开(公告)号：WO0213041A2

    公开(公告)日：2002-02-14

    申请号：PCT/EP0108780

    申请日：2001-07-28

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： KROELL KARL-EUGEN ,  PILLE JUERGEN ,  SCHETTLER HELMUT

    IPC: G06F17/50 ,  G06F19/00 ,  H01L29/00 ,  G06F17/00

    CPC classification number: G06F17/5022 ,  G06F17/5036

    Abstract: An improved hardware circuit simulation method in particular for history-dependent and cyclic operation sensible hardware circuits, like SOI-type hardware, for example, checks for correct cyclic boundary conditions by performing (110) a first run of a prior art DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out (120) a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing (130) the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed (140) before being simulated in vain with a great amount of work and computing time. A transient simulation (150) can be appended for automated correction (160, 170) of dynamic errors.

    Abstract translation: 改进的硬件电路仿真方法，特别是用于历史依赖和循环操作的显性硬件电路（例如，SOI型硬件），例如通过执行（110）先前技术的DC仿真的第一次运行来检查正确的循环边界条件 属于循环启动的电压条件，并通过执行属于循环停止的输入电压条件进行（120）第二次直流模拟。 在比较（130）结果（例如，比较节点电压）之后，可以确定哪些不匹配作为与循环操作不兼容的暗示。 因此，在大量的工作和计算时间被模拟之前，设计能够被重新设计（140）。 可以附加瞬态模拟（150）以进行动态错误的自动校正（160,170）。

    High-speed single end sensing by constructible half latch
    3.
    发明专利
    High-speed single end sensing by constructible half latch 有权
    高速单端感测由构造半长型

    公开(公告)号：JP2000076869A

    公开(公告)日：2000-03-14

    申请号：JP19606299

    申请日：1999-07-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： CLEMEN RAINER ,  MIELICH HERALD ,  PILLE JUERGEN

    IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C29/00

    CPC classification number: G11C7/065 ,  G11C7/067 ,  G11C11/419

    Abstract: PROBLEM TO BE SOLVED: To match and adjust a drift on a bit line to a high-speed system execution mode or low-power test mode in accordance with a feed voltage by using a small skew invertor with a switchable PFET feedback loop.
    SOLUTION: Gate terminals of PFETs P1, P21 are connected to an output of an invertor I1 which is in turn connected to a bit line BL. A signal 'test' is low in a system execution mode. When '1' is to be read from a memory cell, the PFET P1 is turned on and works as a bleeder element to prevent the bit line BL from drifting towards a feed voltage Vdd because of a threshold or smaller current. The signal 'test' is high in a test mode, wherein the PFET P1 works as a keeper element and constitutes a half latch with the invertor I1. The keeper element PFET P1 is reinforced in function by a parallel keeper route of PFETs P21, P22.
    COPYRIGHT: (C)2000,JPO

    Abstract translation: 要解决的问题：通过使用具有可切换PFET反馈回路的小偏斜逆变器，根据馈电电压将位线上的漂移与高速系统执行模式或低功耗测试模式相匹配和调整。 解决方案：PFET P1，P21的栅极端子连接到逆变器I1的输出，反相器I1又连接到位线BL。 信号“测试”在系统执行模式中为低。 当从存储单元读取'1'时，PFET P1导通，并作为泄放元件工作，以防止位线BL由于阈值或更小的电流而向馈送电压Vdd漂移。 信号“测试”在测试模式下很高，其中PFET P1用作保持器元件并且构成具有反相器I1的半锁存器。 保持元件PFET P1通过PFET P21，P22的平行保持器路径功能被加强。

    WRITE/READ DEVICE FOR MEMORY CELL AND ITS METHOD
    4.
    发明专利
    WRITE/READ DEVICE FOR MEMORY CELL AND ITS METHOD 失效

    公开(公告)号：JPH1069772A

    公开(公告)日：1998-03-10

    申请号：JP19820797

    申请日：1997-07-24

    Applicant: IBM

    Inventor： BUETTNER STEFAN ,  PILLE JUERGEN ,  WENDEL DIETER ,  WERNICKE FRIEDRICH

    IPC: G11C11/41 ,  G11C11/419

    Abstract: PROBLEM TO BE SOLVED: To provide a new method restoring a bit line and a data line from a memory cell. SOLUTION: All bit lines (510, 511) and all data lines (517, 518) are connected during a restoration operation, and all restored FET (503, 504, 505) are used for supplying a required recharging current. Successively a non-address specified bit line is turned off by its bit switch. Thus, a size of a recharging device can be made considerably small.

    Unsymmetrischer BIT-Leitungs-Stromerfassungsverstärker für SRAM-Anwendungen
    5.
    发明专利
    Unsymmetrischer BIT-Leitungs-Stromerfassungsverstärker für SRAM-Anwendungen 未知

    公开(公告)号：DE112016002677T5

    公开(公告)日：2018-02-22

    申请号：DE112016002677

    申请日：2016-09-01

    Applicant: IBM

    Inventor： FRITSCH ALEXANDER ,  KALYANASUNDARAM SHANKAR ,  KUGEL MICHAEL B ,  PILLE JUERGEN

    IPC: G11C7/02

    Abstract: Die vorliegende Offenbarung bezieht sich auf einen Stromerfassungs-Leseverstärker zum Verwenden als Leseverstärker bei einer Speicheranordnung von Speicherzellengruppen, wobei in allen Zellen der Speicherzellengruppen wenigstens ein Leseanschluss enthalten ist, der durch eine Bitleitung mit einem Leseverstärker verbunden ist, und wobei die Leseverstärker mit einem Datenausgang verbunden sind. Ein Stromerfassungs-Leseverstärker enthält einen Spannungsregler, um die Bitleitungsspannung auf einem konstanten Spannungswert unterhalb einer Stromversorgungsspannung und oberhalb einer Masse zu halten, eine Messschaltung zum Erkennen eines hohen Stromwerts und eines niedrigen Stromwerts in einem Eingangssignal und einen Generator zum Erzeugen eines Ausgangssignals mit einem hohen Spannungswert, wenn das Eingangssignal mit hohen Stromwert erkannt wird, und zum Erzeugen eines Ausgangssignals mit einem niedrigen Spannungswert, wenn der niedrige Stromwerterkannt wird.

    9.
    发明专利
    未知

    公开(公告)号：DE10110578B4

    公开(公告)日：2004-06-03

    申请号：DE10110578

    申请日：2001-03-06

    Applicant: IBM

    Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

    IPC: G06F13/18 ,  G06F13/26 ,  G06F7/00

    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

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