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    HIGH DENSITY INTEGRATED LOGIC CIRCUIT
    2.
    发明专利
    HIGH DENSITY INTEGRATED LOGIC CIRCUIT 未知

    公开(公告)号：CA1100647A

    公开(公告)日：1981-05-05

    申请号：CA309381

    申请日：1978-08-15

    Applicant: IBM

    Inventor： GANI VENKAPPA L ,  MONTEGARI FRANK A

    IPC: H01L27/082 ,  H01L21/8222 ,  H01L21/8226 ,  H03K19/082 ,  H03K19/173

    Abstract: HIGH DENSITY INTEGRATED LOGIC CIRCUIT The disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell", a plurality of such cells being interconnected to perform desired logic functions. Cell interconnections are made by interconnecting metallurgy which can have a relatively high resistance with relatively long interconnecting paths between a sending circuit cell and a receiving circuit cell. The undesirable effects of this metallurgy resistance are overcome by driving the base of the receiving transistor through a base drive resistor in the sending cell.

    MULTILAYER CAPACITOR
    3.
    发明专利
    MULTILAYER CAPACITOR 未知

    公开(公告)号：CA1290414C

    公开(公告)日：1991-10-08

    申请号：CA595452

    申请日：1989-03-31

    Applicant: IBM

    Inventor： ARNOLD ALLEN J ,  BARIETHER MICHAEL E ,  CHIANG SHIN-WU ,  DALAL HORMAZDYAR M ,  MILLER ROBERT A ,  MONTEGARI FRANK A ,  OBERSCHMIDT JAMES M ,  SHEN DAVID T

    IPC: H01G4/12 ,  H01G4/30 ,  H01G1/005 ,  H01G1/147

    Abstract: Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae including a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that: (a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other. The capacitor finally includes islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs. FI9-88-005

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