公开(公告)号：JPS62103894A

公开(公告)日：1987-05-14

申请号：JP21990786

申请日：1986-09-19

Applicant: IBM

Inventor： JORDY GEORGE JOHN ,  MOONEY DONALD BLAISE ,  MOSLEY JOSEPH MICHAEL

IPC: G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

公开(公告)号：DE3685717D1

公开(公告)日：1992-07-23

申请号：DE3685717

申请日：1986-10-10

Applicant: IBM

Inventor： JORDY GEORGE JOHN ,  MOONEY DONALD BLAISE ,  MOSLEY JOSEPH MICHAEL

IPC: G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

公开(公告)号：DE2963058D1

公开(公告)日：1982-07-29

申请号：DE2963058

申请日：1979-04-24

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI SHIH ,  FOX BARRY CHARLES ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD BLAISE ,  PALMIERI JOHN ALDO

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

公开(公告)号：DE3685717T2

公开(公告)日：1993-01-28

申请号：DE3685717

申请日：1986-10-10

Applicant: IBM

Inventor： JORDY GEORGE JOHN ,  MOONEY DONALD BLAISE ,  MOSLEY JOSEPH MICHAEL

IPC: G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56