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    METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM
    1.
    发明专利
    METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM 未知

    公开(公告)号：CA1075770A

    公开(公告)日：1980-04-15

    申请号：CA280451

    申请日：1977-06-13

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTHER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F11/00

    Abstract: METHOD OF PROPAGATION DELAY TESTING A LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM Propagation delay testing is perfomed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system. The above

    LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM
    2.
    发明专利
    LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM 未知

    公开(公告)号：CA1089031A

    公开(公告)日：1980-11-04

    申请号：CA280452

    申请日：1977-06-13

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTHER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F7/38

    Abstract: LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM A generalized and modular logic system is described for all arithmetic/logical units and their associated control storage and any other arrays. The logic system is partitioned into sections formed of combinational logic networks, storage circuitry, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. The array is a rectangular array of storage element, M x N where, M is the number of words in the array and N is the number of bits in each word. The array may be read only, or it may be a read/write array. The array may be a programmable logic array (PLA). A single- sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic or an array to other latch circuitry. The clocking of the latches and of the array, if any, are such that the network may be operated in a race free mode. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system input/outputs. All of the shift register latches are coupled together into a single shift register. The logic between the latch inputs and the array inputs has the property that a 1 to 1 correspondences can exist between array inputs and the latch inputs. Furthermore, all of the array outputs are uniquely detectable at the latch or primary outputs.

    3.
    发明专利
    未知

    公开(公告)号：FR2356997A1

    公开(公告)日：1978-01-27

    申请号：FR7716797

    申请日：1977-05-26

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F1/04

    Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

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