公开(公告)号：FR2356997A1

公开(公告)日：1978-01-27

申请号：FR7716797

申请日：1977-05-26

Applicant: IBM

Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTER RONALD G ,  WILLIAMS THOMAS W

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F1/04

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.