公开(公告)号：DE3874518D1

公开(公告)日：1992-10-15

申请号：DE3874518

申请日：1988-01-22

Applicant: IBM

Inventor： MUNIER JEAN-MARC ,  PEYRONNENC MICHEL ,  PORET MICHEL

IPC: H04L1/00 ,  G06F11/07 ,  G06F13/40 ,  H04L7/00 ,  G06F11/00

Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.

公开(公告)号：DE3874518T2

公开(公告)日：1993-04-08

申请号：DE3874518

申请日：1988-01-22

Applicant: IBM

Inventor： MUNIER JEAN-MARC ,  PEYRONNENC MICHEL ,  PORET MICHEL

IPC: H04L1/00 ,  G06F11/07 ,  G06F13/40 ,  H04L7/00 ,  G06F11/00

Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.