公开(公告)号：JP2000115199A

公开(公告)日：2000-04-21

申请号：JP24262799

申请日：1999-08-30

Applicant: IBM

Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

IPC: H03M9/00 ,  H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide the connection switch device of a protocol adapter provided with different speed and format characteristics. SOLUTION: This device is provided with a centralized switch core 10 and a switch core access layer element SCAL. Then, the switch core and the SCAL perform communication through the (n) lines of parallel/serial links for transmitting a logic unit. The SCAL is provided with the (n) pieces of FIFOs, the (n) pieces of RAM storage existing together with respective RAMs related to one logic unit, a first multiplex means for performing a write processing under the control of the first set of the (n) pieces of tables and receiving the contents of a parallel bus and a second multiplex means for performing a read processing from the (n) pieces of the RAM storage under the control of the second set of the (n) pieces of the tables and the logic unit is generated.

公开(公告)号：JPS63275241A

公开(公告)日：1988-11-11

申请号：JP5957588

申请日：1988-03-15

Applicant: IBM

Inventor： ROBBE JEAN-CLAUDE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F13/42

公开(公告)号：DE69809224T2

公开(公告)日：2003-08-28

申请号：DE69809224

申请日：1998-08-28

Applicant: IBM

Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

IPC: H03M9/00 ,  H04Q11/04 ,  H04L12/56

Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.

公开(公告)号：DE3874518D1

公开(公告)日：1992-10-15

申请号：DE3874518

申请日：1988-01-22

Applicant: IBM

Inventor： MUNIER JEAN-MARC ,  PEYRONNENC MICHEL ,  PORET MICHEL

IPC: H04L1/00 ,  G06F11/07 ,  G06F13/40 ,  H04L7/00 ,  G06F11/00

Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.

公开(公告)号：DE69737676D1

公开(公告)日：2007-06-14

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：DE3780306D1

公开(公告)日：1992-08-13

申请号：DE3780306

申请日：1987-04-22

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F11/16 ,  G06F11/20

Abstract: A partitioned processing unit is used having two independent processing unit parts (26,28) and a partitioned switching device having two independent switch parts (38,40). Each switch part is associated logically with a corresp. part of the partitioned processing unit. Each processing unit part is connected to an associated group of adapters by a respective primary bus (52,54) and to the group of aoapters of the other unit by a respective secondary bus (46,48). A service processor (14) checks continuously the status of both processing unit parts and if either one fails it controls the bus-switching by operation of the switches (38,40) to maintain all the adaptors connected to whichever processing unit is still working.

公开(公告)号：DE3874518T2

公开(公告)日：1993-04-08

申请号：DE3874518

申请日：1988-01-22

Applicant: IBM

Inventor： MUNIER JEAN-MARC ,  PEYRONNENC MICHEL ,  PORET MICHEL

IPC: H04L1/00 ,  G06F11/07 ,  G06F13/40 ,  H04L7/00 ,  G06F11/00

Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.

公开(公告)号：DE3780306T2

公开(公告)日：1993-02-11

申请号：DE3780306

申请日：1987-04-22

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F11/16 ,  G06F11/20

Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus (52,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.

公开(公告)号：DE3780307D1

公开(公告)日：1992-08-13

申请号：DE3780307

申请日：1987-04-28

Applicant: IBM

Inventor： ROBBE JEAN-CLAUDE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F13/42

Abstract: For safe transmission of signals between a control unit (10) and single card or shared field-replaceable-unit adaptors (18), the link includes one dedicated request line (30) per device, an outgoing Device Control Adaptor Data line (34), an outgoing clock line (38) and two incoming lines (32,36) for request acknowledgements ano Device Data signals. The data lines (34,36) connect the shift register (42) of the control unit (10) to that (44) of the selected device (18), forming a loop (74). The second phase of the protocol is started only after error-free completion of the first.

公开(公告)号：CA1305555C

公开(公告)日：1992-07-21

申请号：CA564155

申请日：1988-04-14

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F11/16 ,  G06F11/20 ,  G06F13/12

Abstract: FR 9 86 020 ADAPTER-BUS SWITCH FOR IMPROVING THE AVAILABILITY OF A CONTROL UNIT A Control Unit is described, including a Processing Unit (1.2) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is: inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus 152,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.