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公开(公告)号：GB2586556A
公开(公告)日：2021-02-24
申请号：GB202018026
申请日：2019-03-28
Applicant: IBM
Inventor： DHARMENDRA SHANTILAL MODHA , JOHN VERNON` ARTHUR , JUN SAWADA , STEVEN KYLE ESSER , RATHINAKUMAR APPUSWAMY , BRIAN SEISHO TABA , ANDREW STEPHEN CASSIDY , PALLAB DATTA , MYRON DALE FLICKNER , HARTMUT PENNER , JENNIFER KLAMO
Abstract: Neural inference chips and cores adapted to provide time, space, and energy efficient neural inference via parallelism and on-chip memory are provided. In various embodiments, the neural inference chips comprise: a plurality of neural cores interconnected by an on-chip network; a first on-chip memory for storing a neural network model, the first on-chip memory being connected to each of the plurality of cores by the on-chip network; a second on-chip memory for storing input and output data, the second on-chip memory being connected to each of the plurality of cores by the on-chip network.
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公开(公告)号：GB2585615A
公开(公告)日：2021-01-13
申请号：GB202016300
申请日：2019-03-11
Applicant: IBM
Inventor： JUN SAWADA , DHARMENDRA SHANTILAL MODHA , JOHN VERNON` ARTHUR , STEVEN KYLE ESSER , BRIAN SEISHO TABA , ANDREW STEPHEN CASSIDY , PALLAB DATTA , MYRON DALE FLICKNER , HARTMUT PENNER , JENNIFER KLAMO , RATHINAKUMAR APPUSWAMY
Abstract: Massively parallel neural inference computing elements are provided. A plurality of multipliers is arranged in a plurality of equal-sized groups. Each of the plurality of multipliers is adapted to, in parallel, apply a weight to an input activation to generate an output. A plurality of adders is operatively coupled to one of the groups of multipliers. Each of the plurality of adders is adapted to, in parallel, add the outputs of the multipliers within its associated group to generate a partial sum. A plurality of function blocks is operatively coupled to one of the plurality of adders. Each of the plurality of function blocks is adapted to, in parallel, apply a function to the partial sum of its associated adder to generate an output value.
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公开(公告)号：GB2586763B
公开(公告)日：2021-08-11
申请号：GB202018196
申请日：2019-03-28
Applicant: IBM
Inventor： ANDREW STEPHEN CASSIDY , MYRON DALE FLICKNER , PALLAB DATTA , HARTMUT PENNER , RATHINAKUMAR APPUSWAMY , JUN SAWADA , JOHN VERNON` ARTHUR , DHARMENDRA SHANTILAL MODHA , STEVEN KYLE ESSER , BRIAN SEISHO TABA , JENNIFER KLAMO
IPC: G06N3/063
Abstract: Neural inference processors are provided. In various embodiments, a processor includes a plurality of cores. Each core includes a neural computation unit, an activation memory, and a local controller. The neural computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The activation memory is adapted to store the input activations and the output activations. The local controller is adapted to load the input activations from the activation memory to the neural computation unit and to store the plurality of output activations from the neural computation unit to the activation memory. The processor includes a neural network model memory adapted to store network parameters, including the plurality of synaptic weights. The processor includes a global scheduler operatively coupled to the plurality of cores, adapted to provide the synaptic weights from the neural network model memory to each core.
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4.发明专利
公开(公告)号：GB2588719A
公开(公告)日：2021-05-05
申请号：GB202017726
申请日：2019-06-05
Applicant: IBM
Inventor： ANDREW STEPHEN CASSIDY , MYRON DALE FLICKNER , PALLAB DATTA , HARTMUT PENNER , RATHINAKUMAR APPUSWAMY , JUN SAWADA , JOHN VERNON` ARTHUR , JENNIFER KLAMO , BRIAN SEISHO TABA , STEVEN KYLE ESSER , DHARMENDRA SHANTILAL MODHA
Abstract: Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.
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公开(公告)号：SG90188A1
公开(公告)日：2002-07-23
申请号：SG200006269
申请日：2000-10-31
Applicant: IBM
Inventor： ERIC GORDON BAUGH , MYRON DALE FLICKNER , ROBERT EDWARD FONTANA JR , STEPHEN ARNOLD OLSON , GURINDER PAL SINGH
Abstract: A method and tool for measurement of the roll static attitude and y-misalignment of magnetic recording sliders within the head stack assembly having reference elements placed on the deposited end of the magnetic recording slider, which are optically analyzed by a video camera connected to a computer. For fast measurement the head stack assembly is clamped in a fixture mounted on motorized stages, which move each slider into the measurement position. In a two step imaging and analyzing process, the orientation and location of one or more edges of the reference element are computed and compared with known control parameters.
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Patent Agency Ranking
公开(公告)号：GB2585615B
公开(公告)日：2021-05-19
申请号：GB202016300
申请日：2019-03-11
Applicant: IBM
Inventor： JUN SAWADA , DHARMENDRA SHANTILAL MODHA , JOHN VERNON` ARTHUR , STEVEN KYLE ESSER , BRIAN SEISHO TABA , ANDREW STEPHEN CASSIDY , PALLAB DATTA , MYRON DALE FLICKNER , HARTMUT PENNER , JENNIFER KLAMO , RATHINAKUMAR APPUSWAMY
Abstract: Massively parallel neural inference computing elements are provided. A plurality of multipliers is arranged in a plurality of equal-sized groups. Each of the plurality of multipliers is adapted to, in parallel, apply a weight to an input activation to generate an output. A plurality of adders is operatively coupled to one of the groups of multipliers. Each of the plurality of adders is adapted to, in parallel, add the outputs of the multipliers within its associated group to generate a partial sum. A plurality of function blocks is operatively coupled to one of the plurality of adders. Each of the plurality of function blocks is adapted to, in parallel, apply a function to the partial sum of its associated adder to generate an output value.
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公开(公告)号：GB2553451A
公开(公告)日：2018-03-07
申请号：GB201716188
申请日：2016-01-22
Applicant: IBM
Inventor： ARNON AMIR , RATHINAKUMAR APPUSWAMY , PALLAB DATTA , BENJAMIN GORDON SHAW , MYRON DALE FLICKNER , PAUL MEROLLA , DHARMENDRA SHANTILAL MODHA
Abstract: One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.
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公开(公告)号：GB2586556B
公开(公告)日：2021-08-11
申请号：GB202018026
申请日：2019-03-28
Applicant: IBM
Inventor： DHARMENDRA SHANTILAL MODHA , JOHN VERNON` ARTHUR , JUN SAWADA , STEVEN KYLE ESSER , RATHINAKUMAR APPUSWAMY , BRIAN SEISHO TABA , ANDREW STEPHEN CASSIDY , PALLAB DATTA , MYRON DALE FLICKNER , HARTMUT PENNER , JENNIFER KLAMO
Abstract: Neural inference chips and cores adapted to provide time, space, and energy efficient neural inference via parallelism and on-chip memory are provided. In various embodiments, the neural inference chips comprise: a plurality of neural cores interconnected by an on-chip network; a first on-chip memory for storing a neural network model, the first on-chip memory being connected to each of the plurality of cores by the on-chip network; a second on-chip memory for storing input and output data, the second on-chip memory being connected to each of the plurality of cores by the on-chip network.
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公开(公告)号：GB2587175A
公开(公告)日：2021-03-17
申请号：GB202100512
申请日：2019-06-13
Applicant: IBM
Inventor： ANDREW STEPHEN CASSIDY , PALLAB DATTA , JENNIFER KLAMO , JUN SAWADA , RATHINAKUMAR APPUSWAMY , STEVEN KYLE ESSER , DHARMENDRA SHANTILAL MODHA , BRIAN SEISHO TABA , JOHN VERNON` ARTHUR , MYRON DALE FLICKNER , HARTMUT PENNER
Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.
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公开(公告)号：GB2586763A
公开(公告)日：2021-03-03
申请号：GB202018196
申请日：2019-03-28
Applicant: IBM
Inventor： ANDREW STEPHEN CASSIDY , MYRON DALE FLICKNER , PALLAB DATTA , HARTMUT PENNER , RATHINAKUMAR APPUSWAMY , JUN SAWADA , JOHN VERNON` ARTHUR , DHARMENDRA SHANTILAL MODHA , STEVEN KYLE ESSER , BRIAN SEISHO TABA , JENNIFER KLAMO
IPC: G06N3/063
Abstract: Neural inference processors are provided. In various embodiments, a processor includes a plurality of cores. Each core includes a neural computation unit, an activation memory, and a local controller. The neural computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The activation memory is adapted to store the input activations and the output activations. The local controller is adapted to load the input activations from the activation memory to the neural computation unit and to store the plurality of output activations from the neural computation unit to the activation memory. The processor includes a neural network model memory adapted to store network parameters, including the plurality of synaptic weights. The processor includes a global scheduler operatively coupled to the plurality of cores, adapted to provide the synaptic weights from the neural network model memory to each core.
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