METHOD AND SYSTEM FOR MULTIPROCESSING
    5.
    发明专利

    公开(公告)号:JP2002312190A

    公开(公告)日:2002-10-25

    申请号:JP2002042057

    申请日:2002-02-19

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessing system, operating in a high reliability mode to detect computational errors. SOLUTION: This multiprocessing system includes a first processor, a second processor, and a compare logic. The first processor is operable to compute first results responsive to instructions, the second processor is operable to compute second results responsive to the instructions, and the compare logic is operable to check at check points for matching of the results. Each of the processors has a first register for storing one of the processor's results, and the register has a stack of shadow registers. The processor is operable to shift a current one of the processor's results from the first register into the top shadow register, so that an earlier one of the processor's results can be restored from one of the shadow registers to the first register, responsive to the compare logic determining that the first and second results mismatch.

    METHOD AND APPARATUS FOR COMPUTER SYSTEM RELIABILITY

    公开(公告)号:CA2367793A1

    公开(公告)日:2002-08-22

    申请号:CA2367793

    申请日:2002-01-15

    Applicant: IBM

    Abstract: According to one embodiment, a multiprocessing system includes a first processor, a second processor, and compare logic. The first processor is operable to compute fir st results responsive to instructions, the second processor is operable to compute second results responsive to the instructions, and the compare logic is operable to check at checkpoints for matching of the results. Each of the processors has a first register for storing one of the processor 's results, and the register has a stack of shadow registers. The processor is operable to shift a curren t one of the processor's results from the first register into the top shadow register, so that an earlier one of the processor's results can be restored from one of the shadow registers to the first regist er responsive to the compare logic determining that the first and second results mismatch. It is advantageous that the shadow register stack is closely coupled to its corresponding register, which provides for fast restoration of results. In a further aspect of an embodiment, each processor has a signatur e generator and a signature storage unit. The signature generator and storage units are operab le to cooperatively compute a cumulative signature for a sequence of the processor's results, an d the processor is operable to store the cumulative signature in the signature storage unit pending the match or mismatch determination by the compare logic. The checking for matching of th e results includes the compare logic comparing the cumulative signatures of each respective processor. It is faster, and therefore advantageous, to check respective cumulative signatures at interva ls rather than to check each individual result.

    RATIONALISIEREN VON DATENVERARBEITUNGSOPTIMIERUNGEN FÜR ARBEITSLASTEN MIT MASCHINELLEM LERNEN

    公开(公告)号:DE112021001767T5

    公开(公告)日:2023-01-12

    申请号:DE112021001767

    申请日:2021-05-14

    Applicant: IBM

    Abstract: Bereitgestellt werden Methoden zur Verfeinerung von Daten-Pipelines. Eine ursprüngliche Datei von serialisierten Objekten wird empfangen, und eine ursprüngliche Pipeline, die eine Mehrzahl von Transformationen aufweist, wird auf Grundlage der ursprünglichen Datei identifiziert. Für eine erste Transformation der Mehrzahl von Transformationen werden erste Datenverarbeitungskosten ermittelt. Die erste Transformation wird unter Verwendung einer vordefinierten Optimierung modifiziert, und zweite Kosten der modifizierten ersten Transformation werden ermittelt. Wenn ermittelt wird, dass die zweiten Kosten niedriger als die ersten Kosten sind, wird die erste Transformation in der ursprünglichen Pipeline durch die optimierte erste Transformation ersetzt.

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