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    Monolithic storage multi-emitter transistors with different width bases
    1.
    发明授权
    Monolithic storage multi-emitter transistors with different width bases 失效
    具有不同宽度基础的单片存储多发射体晶体管

    公开(公告)号：US3810123A

    公开(公告)日：1974-05-07

    申请号：US26732472

    申请日：1972-06-29

    Applicant: IBM

    Inventor： BAITINGER U ,  NAJMANN K

    IPC: G11C11/411 ,  H01L27/082 ,  H01L27/102 ,  G11C11/40

    CPC classification number: H01L27/0825 ,  G11C11/4116 ,  H01L27/1025 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145

    Abstract: A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.

    Abstract translation: 一种单片存储矩阵，其具有由多发射极晶体管形成的单元，其中每个晶体管的一个发射极构成存储电路的一部分，并且每个晶体管的另一个发射极耦合到存取和恢复电路。 用于存储的晶体管部分形成为具有给定宽度的基极，并且耦合到访问和检索电路的晶体管部分具有较小的宽度，使得在保持存储电路的稳定性的同时获得短的访问时间。

    Monolithic bipolar transistor storage arrangement with latent bit pattern
    2.
    发明授权
    Monolithic bipolar transistor storage arrangement with latent bit pattern 失效
    单晶双极晶体管存储装置与专利位图案

    公开(公告)号：US3801967A

    公开(公告)日：1974-04-02

    申请号：US3801967D

    申请日：1973-02-12

    Applicant: IBM

    Inventor： BERGER H ,  NAJMANN K ,  PIETRASS H ,  WIEDMANN S

    IPC: G11C7/20 ,  G11C11/411 ,  G11C17/08 ,  H01L27/102 ,  H03K3/286 ,  H03K3/356 ,  G11C11/40 ,  G11C13/00 ,  H03K3/281

    CPC classification number: H01L27/1025 ,  G11C7/20 ,  G11C11/4113 ,  G11C17/08 ,  H03K3/2865 ,  H03K3/356008

    Abstract: A monolithic storage arrangement comprising a plurality of cross-coupled bipolar transistor bistable storage cells selectively operable both as a read-write storage and as a readonly storage. The switching nodes of each storage cell are connected to respective switching bipolar transistors which are complementary with respect to the cross-coupled transistors, the collector-base section of the switching transistors being connected in parallel with the base-emitter section of the respective cross-coupled transistors. For read-only operation, the emitter of one of the switching transistors is connected to a control line with the emitter of the other switching transistor remaining unconnected in accordance with predetermined fabrication personalization. The connected switching transistor injects current into the base of its associated cross-coupled transistor when the control line is suitably energized to place the cell into a desired read-only state. Both switching transistors are deactivated during read-write operation.

    Abstract translation: 一种单片存储装置，包括可选择性地兼作读写存储器和只读存储器的多个交叉耦合双极晶体管双稳态存储单元。 每个存储单元的开关节点连接到相对于交叉耦合晶体管互补的相应的开关双极晶体管，开关晶体管的集电极 - 基极部分与各自的交叉耦合晶体管的基极 - 发射极部分并联连接， 耦合晶体管。 对于只读操作，其中一个开关晶体管的发射极根据预定的制造个性化被连接到控制线，而另一个开关晶体管的发射极保持未连接。 当控制线被适当地通电以将电池置于期望的只读状态时，连接的开关晶体管将电流注入到其相关联的交叉耦合晶体管的基极中。 在读写操作期间，两个开关晶体管都被禁止。

    4.
    发明专利
    未知

    公开(公告)号：SE345537B

    公开(公告)日：1972-05-29

    申请号：SE587669

    申请日：1969-04-25

    Applicant: IBM

    Inventor： FRANTZ H ,  NAJMANN K

    IPC: G11C11/411 ,  H01L27/06 ,  H01L27/07 ,  H03K3/288 ,  G05F1/50 ,  H02J1/00

    Abstract: 1,245,368. Semiconductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 28 March, 1969 [30 April, 1968], No. 16392/69. Heading H1K. [Also in Division H3] In a monolithic integrated circuit two transistors are formed in a common epitaxial region, which forms a part of each transistor, by means of separate diffused regions, the transistors being connected in a circuit so that in operation the common region functions as the emitter of at least one of the transistors. The transistors are formed simultaneously by diffusing P-type base regions into an N-type epitaxial layer on a P+-type substrate, the epitaxial layer being divided into islands by a P-type isolation diffusion. N-type regions are diffused into the base regions and form the emitters of normally poled transistors and the collectors of inversely poled transistors. The inversely poled transistors exhibit a low gain which may be less than unity if the circuit is gold doped. A memory cell, Fig. 3, comprises five transistors T1 to T5 and two resistors R1 and R2, two of the transistors T3, T4, forming a bi-stable multivibrator, being arranged in a single island and operated so that the common region functions as their emitters, and the other three transistors T1, T2, T5, forming addressing, reading and writing components, being arranged in a second island and operated so that the common region forms the emitters of two of the transistors T1, T2 and the collector of the third transistor T5.

    6.
    发明专利
    未知

    公开(公告)号：FR1419960A

    公开(公告)日：1965-12-03

    申请号：FR997369

    申请日：1964-12-04

    Applicant: IBM

    Inventor： NAJMANN K

    IPC: G04G3/02 ,  H03K21/00

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