公开(公告)号：KR800001342B1

公开(公告)日：1980-10-28

申请号：KR760000527

申请日：1976-03-04

Applicant: IBM

Inventor： WIEDMANN S ,  BERGER H

IPC: H01L27/04

Abstract: The disclosure is directed to the circuitry and monolithic semiconductor structure of current Hogging injection logic configurations. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multicollector inverter transistors which are fed by means of a carrier injection into their emitter/base zones.

公开(公告)号：US3801967A

公开(公告)日：1974-04-02

申请号：US3801967D

申请日：1973-02-12

Applicant: IBM

Inventor： BERGER H ,  NAJMANN K ,  PIETRASS H ,  WIEDMANN S

IPC: G11C7/20 ,  G11C11/411 ,  G11C17/08 ,  H01L27/102 ,  H03K3/286 ,  H03K3/356 ,  G11C11/40 ,  G11C13/00 ,  H03K3/281

CPC classification number: H01L27/1025 ,  G11C7/20 ,  G11C11/4113 ,  G11C17/08 ,  H03K3/2865 ,  H03K3/356008

Abstract: A monolithic storage arrangement comprising a plurality of cross-coupled bipolar transistor bistable storage cells selectively operable both as a read-write storage and as a readonly storage. The switching nodes of each storage cell are connected to respective switching bipolar transistors which are complementary with respect to the cross-coupled transistors, the collector-base section of the switching transistors being connected in parallel with the base-emitter section of the respective cross-coupled transistors. For read-only operation, the emitter of one of the switching transistors is connected to a control line with the emitter of the other switching transistor remaining unconnected in accordance with predetermined fabrication personalization. The connected switching transistor injects current into the base of its associated cross-coupled transistor when the control line is suitably energized to place the cell into a desired read-only state. Both switching transistors are deactivated during read-write operation.

Abstract translation: 一种单片存储装置，包括可选择性地兼作读写存储器和只读存储器的多个交叉耦合双极晶体管双稳态存储单元。 每个存储单元的开关节点连接到相对于交叉耦合晶体管互补的相应的开关双极晶体管，开关晶体管的集电极 - 基极部分与各自的交叉耦合晶体管的基极 - 发射极部分并联连接， 耦合晶体管。 对于只读操作，其中一个开关晶体管的发射极根据预定的制造个性化被连接到控制线，而另一个开关晶体管的发射极保持未连接。 当控制线被适当地通电以将电池置于期望的只读状态时，连接的开关晶体管将电流注入到其相关联的交叉耦合晶体管的基极中。 在读写操作期间，两个开关晶体管都被禁止。

公开(公告)号：US3729719A

公开(公告)日：1973-04-24

申请号：US3729719D

申请日：1970-11-27

Applicant: IBM

Inventor： WIEDMANN S

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102 ,  G11C11/24 ,  G11C11/40

CPC classification number: H01L27/1023 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/075 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: This specification discloses a stored charge storage cell for monolithic memories. The cell comprises a device akin to a silicon-controlled rectifier and can be schematically illustrated as an NPN and a PNP transistor connected together in what is commonly called a hook circuit. A fixed potential is applied to the semiconductor zone of the device not commonly used as a terminal for a silicon-controlled rectifier so that the cell is prevented from latching as a silicon-controlled rectifier or hook circuit would normally latch. The charge on the capacitance of collector-base PN junctions of the NPN and PNP transistors is then controlled to store data in the cell.

Abstract translation: 本说明书公开了一种用于单片存储器的存储电荷存储单元。 电池包括类似于可控硅整流器的器件，并且可以示意性地示出为以通常称为钩形电路连接在一起的NPN和PNP晶体管。 固定电位被施加到不通常用作硅可控整流器的端子的器件的半导体区域，使得由于可控硅整流器或钩形电路将正常地锁存而防止电池闭锁。 然后控制NPN和PNP晶体管的集电极 - 基极PN结电容的电荷，以将数据存储在电池中。

公开(公告)号：US3816758A

公开(公告)日：1974-06-11

申请号：US34142473

申请日：1973-03-15

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S

IPC: G11C11/411 ,  G11C11/415 ,  H01L27/02 ,  H01L27/082 ,  H01L27/102 ,  H03K19/091 ,  H03K19/40 ,  H03K19/34

CPC classification number: H01L27/0821 ,  G11C11/4113 ,  G11C11/415 ,  H01L27/0233 ,  H01L27/1022 ,  H01L27/1025 ,  H03K19/091

Abstract: A monolithic semiconductor circuit comprises a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semi-conductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.

Abstract translation: 单片半导体电路包括横向PNP晶体管和反向操作的垂直NPN晶体管。 横向晶体管由扩散在N型半导体本体中的一对相互间隔开的P型区域形成。 集电极区域在其中扩散了N型区域并构成垂直晶体管的集电极。 半导体体构成横向晶体管的基极区域和垂直晶体管的发射极区域。

公开(公告)号：US3736477A

公开(公告)日：1973-05-29

申请号：US3736477D

申请日：1971-04-14

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S

IPC: G11C11/40 ,  G11C11/411 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H03K19/091 ,  H01L19/00

CPC classification number: H03K19/091 ,  G11C11/40 ,  G11C11/4113 ,  H01L27/0233 ,  H01L27/0821

Abstract: A monolithic semiconductor circuit comprises a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semiconductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.

Abstract translation: 单片半导体电路包括横向PNP晶体管和反向操作的垂直NPN晶体管。 横向晶体管由扩散在N型半导体本体中的一对相互间隔开的P型区域形成。 集电极区域在其中扩散了N型区域并构成垂直晶体管的集电极。 半导体主体构成横向晶体管的基极区域和垂直晶体管的发射极区域。

公开(公告)号：US3823353A

公开(公告)日：1974-07-09

申请号：US33751073

申请日：1973-03-02

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732 ,  H03K19/091 ,  H03K19/098 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L29/7327 ,  H01L27/0237 ,  H01L27/0688 ,  H03K19/091 ,  H03K19/098 ,  Y10S148/037 ,  Y10S148/085

Abstract: Logic circuits for performing the INVERTER and NOR functions, and monolithic integrated structures for realizing the circuits. The basic circuit comprises PNP transistor and an NPN transistor. The emitter of the PNP transistor has its base grounded and its collector connected to the base of the NPN transistor having its emitter grounded. The logic signal input is at the base of the NPN transistor. The output is taken at the collector of the NPN transistor and is the inverse of the input. Two such basic circuits are interconnected to provide the NOR function.

公开(公告)号：US3770519A

公开(公告)日：1973-11-06

申请号：US3770519D

申请日：1970-08-05

Applicant: IBM

Inventor： WIEDMANN S

IPC: H01L21/761 ,  H01L27/00 ,  H01L27/07 ,  H01L7/36 ,  H01L7/44 ,  H01L19/00

CPC classification number: H01L27/0761 ,  H01L21/761 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/151

Abstract: A method for making reduced beta transistors within one of a plurality of isolated regions of a microcircuit structure. The beta reduction is accomplished by using standard isolation diffusion technology modified only to the extent of opening a hole in the isolation diffusion mask at the base location of each desired reduced beta transistor having a subcollector. The isolation impurity, being of the same conductivity type as the base diffusion and being of relatively high impurity concentration, reduces the emitter efficiency of each desired reduced beta transistor to an extent whereby the reduced beta transistor functions substantially as a self-isolated diode. Self-isolation of the diodes is achieved utilizing a minimum of microcircuit device surface area by elimination of separate isolating regions for the resulting diodes.

Abstract translation: 一种用于在微电路结构的多个隔离区域之一内制造还原的β晶体管的方法。 β还原是通过使用标准隔离扩散技术来实现的，该技术仅在每个具有子集电极的所需还原β晶体管的基极位置处的隔离扩散掩模中打开孔的程度。 具有与基底扩散相同的导电类型并且具有相对高的杂质浓度的隔离杂质将每个所需的还原β晶体管的发射极效率降低到一个程度，从而减小的β晶体管基本上起到自隔离二极管的作用。 通过消除所得到的二极管的单独的隔离区域，利用最小的微电路器件表面积来实现二极管的自隔离。

公开(公告)号：BR7707519A

公开(公告)日：1978-08-01

申请号：BR7707519

申请日：1977-11-09

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S

IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/08

Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I2L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

公开(公告)号：BR7601316A

公开(公告)日：1976-09-14

申请号：BR7601316

申请日：1976-03-04

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S

IPC: G06F7/00

公开(公告)号：CA934071A

公开(公告)日：1973-09-18

申请号：CA134680

申请日：1972-02-14

Applicant: IBM

Inventor： BERGER H ,  WIEDMANN S