Abstract:
A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.
Abstract:
A planar monolithic circuit is made with a plurality of transistors in a single isolated region in a common emitter circuit configuration. An N-type epitaxial layer constitutes the emitter region into which the base regions of a P-type material are subsequently diffused, and an N-type collector is then diffused into the base regions forming NPN transistors. The Ntype epitaxial region can simultaneously be the common collector region for some of the transistors and the common emitter region for other ones of the transistor in an operative circuit arrangement. Three transistors in a single isolated region can be formed in the shape of an ''''L'''' so that when two of these are interlinked, a rectangle is formed.