公开(公告)号：US3866176A

公开(公告)日：1975-02-11

申请号：US43815974

申请日：1974-01-31

Applicant: IBM

Inventor： BAITINGER UTZ G ,  HAUG WERNER OTTO ,  ILLI MANFRED

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  H04Q3/00

CPC classification number: G11C11/418 ,  G11C5/00 ,  G11C8/18 ,  G11C11/415 ,  G11C11/417 ,  H03M7/00

Abstract: For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders. An automatic optimum determination of the conditioning time of the AND gates at the outputs of phase splitters is achieved by a delayed clock pulse DCS1 derived from a clock pulse T of AND gates at the input of the phase splitters. For that purpose, clock pulse T is derived at the output of the AND gates at the input of phase splitters and, via a simulated phase splitter circuit integrated on the chip, is applied as clock pulse DCS1 to the clock inputs of the AND gates at the output of the functional phase splitters. The determination of the conditioning time of AND gates at the output of the decoder is performed accordingly at the output of decoder. In that process, a clock signal is derived from the output of AND gates at the output of phase splitters, and applied as a delayed clock signal DCS2 via a simulation of one of decoders to the clock inputs of the AND gates at the output of the decoders.

Abstract translation: 对于编码地址的每个二进制位置，选择装置示出了一个相位分离器，其两个输出端连接到解码器的相关输入端。 为了提高联合时钟的噪声电阻，并且门分别插入在相位分离器的输入和输出端以及解码器的输出端。

公开(公告)号：US3884732A

公开(公告)日：1975-05-20

申请号：US39804073

申请日：1973-09-17

Applicant: IBM

Inventor： BAITINGER UTZ G ,  NAJMANN KNUT K

IPC: G11C11/411 ,  H01L27/102 ,  H01L29/10 ,  H01L7/44 ,  H01L7/64 ,  H01L29/72

CPC classification number: H01L29/1004 ,  G11C11/4116 ,  H01L27/1025 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151

Abstract: A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.

公开(公告)号：CA1031041A

公开(公告)日：1978-05-09

申请号：CA205112

申请日：1974-07-17

Applicant: IBM

Inventor： BAITINGER UTZ G ,  HAUG WERNER O ,  ILLI MANFRED

IPC: G11C11/41 ,  G11C20060101 ,  G11C8/00 ,  G11C11/34 ,  G11C11/413 ,  H04Q9/14

公开(公告)号：CA1005930A

公开(公告)日：1977-02-22

申请号：CA203550

申请日：1974-06-27

Applicant: IBM

Inventor： BAITINGER UTZ G ,  FOLBERTH OTTO G ,  HAUG WERNER ,  KROELL KARL-EUGEN

IPC: H01L21/8234 ,  H01L21/331 ,  H01L27/06 ,  H01L27/088 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/78