公开(公告)号：DE69631012T2

公开(公告)日：2004-08-05

申请号：DE69631012

申请日：1996-09-23

Applicant: IBM

Inventor： MATSUSHIMA SHINJI ,  KAWANO SEIICHI ,  NAKANO MASAYOSHI ,  INUI TAKASHI

IPC: G06F1/04 ,  G06F1/32 ,  G06F3/06

Abstract: An information processing system achieves power saving by reducing the operating frequency of a CPU, or completely halting the operation of the CPU, at appropriate times during asynchronous communication with peripheral devices. The information processing system comprises: (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) termination detection means for detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) time counting means for measuring a predetermined period of time after the completion of the predetermined transaction; and (f) power saving control means for having the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

公开(公告)号：DE69630851D1

公开(公告)日：2004-01-08

申请号：DE69630851

申请日：1996-09-16

Applicant: IBM

Inventor： INUI TAKASHI ,  KAWANO SEIICHI ,  MATSUSHIMA SHINJI ,  NAKANO MASAYOSHI ,  SHIRAISHI YUICHI

IPC: G06F1/32

公开(公告)号：DE69630851T2

公开(公告)日：2004-09-02

申请号：DE69630851

申请日：1996-09-16

Applicant: IBM

Inventor： INUI TAKASHI ,  KAWANO SEIICHI ,  MATSUSHIMA SHINJI ,  NAKANO MASAYOSHI ,  SHIRAISHI YUICHI

IPC: G06F1/32

公开(公告)号：DE69631012D1

公开(公告)日：2004-01-22

申请号：DE69631012

申请日：1996-09-23

Applicant: IBM

Inventor： MATSUSHIMA SHINJI ,  KAWANO SEIICHI ,  NAKANO MASAYOSHI ,  INUI TAKASHI

IPC: G06F1/04 ,  G06F1/32 ,  G06F3/06

Abstract: An information processing system achieves power saving by reducing the operating frequency of a CPU, or completely halting the operation of the CPU, at appropriate times during asynchronous communication with peripheral devices. The information processing system comprises: (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) termination detection means for detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) time counting means for measuring a predetermined period of time after the completion of the predetermined transaction; and (f) power saving control means for having the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.